参数资料
| 型号： | EPF10K130EQI240-2 |
| 厂商： | Altera |
| 文件页数： | 33/100页 |
| 文件大小： | 0K |
| 描述： | IC FLEX 10KE FPGA 130K 240-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 24 |
| 系列： | FLEX-10KE® |
| LAB/CLB数： | 832 |
| 逻辑元件/单元数： | 6656 |
| RAM 位总计： | 65536 |
| 输入/输出数： | 186 |
| 门数： | 342000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
| 其它名称： | 544-2206 |
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38
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
ClockLock &
ClockBoost
Features
To support high-speed designs, FLEX 10KE devices offer optional
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
used to increase design speed and reduce resource usage. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by resource sharing within the device. The ClockBoost feature
allows the designer to distribute a low-speed clock and multiply that clock
on-device. Combined, the ClockLock and ClockBoost features provide
significant improvements in system performance and bandwidth.
All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices,
support ClockLock and ClockBoost circuitry. EPF10K50S and
EPF10K200S devices support this circuitry. Devices that support Clock-
Lock and ClockBoost circuitry are distinguished with an “X” suffix in the
ordering code; for instance, the EPF10K200SFC672-1X device supports
this circuit.
The ClockLock and ClockBoost features in FLEX 10KE devices are
enabled through the Altera software. External devices are not required to
use these features. The output of the ClockLock and ClockBoost circuits is
not available at any of the device pins.
The ClockLock and ClockBoost circuitry locks onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the
Altera software, the GCLK1 pin can feed both the ClockLock and
ClockBoost circuitry in the FLEX 10KE device. However, when both
circuits are used, the other clock pin cannot be used.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K130EQI240-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 832 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K130V | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| EPF10K130VBC600-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K130VBC600-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K130VBC600-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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