参数资料
型号: EPM7064BFC100-5
厂商: ALTERA CORP
元件分类: PLD
英文描述: EE PLD, 3.5 ns, PBGA100
封装: FBGA-100
文件页数: 1/66页
文件大小: 962K
代理商: EPM7064BFC100-5
Altera Corporation
1
MAX 7000B
Programmable Logic
Device
September 2005, ver. 3.5
Data Sheet
DS-MAX7000B-3.5
Features...
High-performance 2.5-V CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX) architecture (see Table 1)
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
High-density PLDs ranging from 600 to 10,000 usable gates
3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Advanced 2.5-V in-system programmability (ISP)
Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in-system programming
ISP circuitry compliant with IEEE Std. 1532
f For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
Table 1. MAX 7000B Device Features
Feature
EPM7032B
EPM7064B
EPM7128B
EPM7256B
EPM7512B
Usable gates
600
1,250
2,500
5,000
10,000
Macrocells
32
64
128
256
512
Logic array blocks
2
4
8
16
32
Maximum user I/O
pins
36
68
100
164
212
tPD (ns)
3.5
4.0
5.0
5.5
tSU (ns)
2.1
2.5
3.3
3.6
tFSU (ns)
1.0
tCO1 (ns)
2.4
2.8
3.3
3.7
fCNT (MHz)
303.0
243.9
188.7
163.9
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相关代理商/技术参数
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EPM7064BTC100-3 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100