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| 型号： | EPM7064BFC100-5 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 3.5 ns, PBGA100 |
| 封装： | FBGA-100 |
| 文件页数： | 45/66页 |
| 文件大小： | 962K |
| 代理商： | EPM7064BFC100-5 |
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Altera Corporation
5
MAX 7000B Programmable Logic Device Data Sheet
MAX 7000B devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate up to 50% lower power while adding only
a nominal timing delay. MAX 7000B devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000B devices can be set for 3.3 V, 2.5 V, or 1.8 V and all input pins
are 3.3-V, 2.5-V, and 1.8-V tolerant, allowing MAX 7000B devices to be
used in mixed-voltage systems.
MAX 7000B devices are supported by Altera development systems, which
are integrated packages that offer schematic, text—including VHDL,
Verilog HDL, and the Altera Hardware Description Language (AHDL)—
and waveform design entry, compilation and logic synthesis, simulation
and timing analysis, and device programming. Altera software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. Altera software
runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000
Series 700/800 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
The MAX 7000B architecture includes the following elements:
■
LABs
■
Macrocells
■
Expander product terms (shareable and parallel)
■
PIA
■
I/O control blocks
The MAX 7000B architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000B devices.
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| EPM7064BFC100-7 | EE PLD, 3.5 ns, PBGA100 |
| EPM7064BTC100-3 | EE PLD, 3.5 ns, PQFP100 |
| EPM7064BTC100-5 | EE PLD, 3.5 ns, PQFP100 |
| EPM7064BTC100-7 | EE PLD, 3.5 ns, PQFP100 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7064BFC100-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7064BLC44-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BLC44-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BLC44-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BTC100-3 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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