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参数资料
| 型号： | EPM7064BFC100-5 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | EE PLD, 3.5 ns, PBGA100 |
| 封装： | FBGA-100 |
| 文件页数： | 65/66页 |
| 文件大小： | 962K |
| 代理商： | EPM7064BFC100-5 |
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8
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
Global clock signal. This mode achieves the fastest clock-to-output
performance.
■
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
■
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000B devices. As shown
in Figure 1, these global clock signals can be the true or the complement of
either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000B
device may be set to either a high or low state. This power-up state is
specified at design entry.
All MAX 7000B I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast input
setup time. The input path from the I/O pin to the register has a
programmable delay element that can be selected to either guarantee zero
hold time or to get the fastest possible set-up time (as fast as 1.0 ns).
相关PDF资料 |
PDF描述 |
|---|---|
| EPM7064BFC100-7 | EE PLD, 3.5 ns, PBGA100 |
| EPM7064BTC100-3 | EE PLD, 3.5 ns, PQFP100 |
| EPM7064BTC100-5 | EE PLD, 3.5 ns, PQFP100 |
| EPM7064BTC100-7 | EE PLD, 3.5 ns, PQFP100 |
| EPM7064BTC44-3 | EE PLD, 3.5 ns, PQFP44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPM7064BFC100-7 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| EPM7064BLC44-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BLC44-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BLC44-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BTC100-3 | 功能描述:CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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