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| 型号： | EPM9560ARI240-10 |
| 厂商： | Altera |
| 文件页数： | 4/46页 |
| 文件大小： | 0K |
| 描述： | IC MAX 9000 CPLD 560 240-RQFP |
| 产品变化通告： | Package Change 30/Jun/2010 |
| 标准包装： | 24 |
| 系列： | Max® 9000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 10.0ns |
| 电压电源 - 内部： | 4.5 V ~ 5.5 V |
| 逻辑元件/逻辑块数目： | 35 |
| 宏单元数： | 560 |
| 门数： | 12000 |
| 输入/输出数： | 191 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BFQFP 裸露焊盘 |
| 供应商设备封装： | 240-RQFP（32x32） |
| 包装： | 托盘 |
| 其它名称： | 544-2365 |
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12
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
The MAX+PLUS II Compiler automatically allocates as many as three sets
of up to five parallel expanders to macrocells that require additional
product terms. Each set of expanders incurs a small, incremental timing
delay (tPEXP). For example, if a macrocell requires 14 product terms, the
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2
× t
PEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them.
FastTrack Interconnect
In the MAX 9000 architecture, connections between macrocells and device
I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
entire device. This device-wide routing structure provides predictable
performance even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance. Figure 6 shows the interconnection of four adjacent LABs
with row and column interconnects.
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