参数资料
型号: EPM9560ARI240-10
厂商: Altera
文件页数: 9/46页
文件大小: 0K
描述: IC MAX 9000 CPLD 560 240-RQFP
产品变化通告: Package Change 30/Jun/2010
标准包装: 24
系列: Max® 9000
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 4.5 V ~ 5.5 V
逻辑元件/逻辑块数目: 35
宏单元数: 560
门数: 12000
输入/输出数: 191
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 240-BFQFP 裸露焊盘
供应商设备封装: 240-RQFP(32x32)
包装: 托盘
其它名称: 544-2365
Altera Corporation
17
MAX 9000 Programmable Logic Device Family Data Sheet
Figure 10. MAX 9000 IOC
I/O pins can be used as input, output, or bidirectional pins. Each IOC has
an IOC register with a clock enable input. This register can be used either
as an input register for external data that requires fast setup times, or as an
output register for data that requires fast clock-to-output performance.
The IOC register clock enable allows the global clock to be used for fast
clock-to-output performance, while maintaining the flexibility required
for selective clocking.
The clock, clock enable, clear, and output enable controls for the IOCs are
provided by a network of I/O control signals. These signals can be
supplied by either the dedicated input pins or internal logic. The IOC
control-signal paths are designed to minimize the skew across the device.
All control-signal sources are buffered onto high-speed drivers that drive
the signals around the periphery of the device. This “peripheral bus” can
be configured to provide up to eight output enable signals, up to four
clock signals, up to six clock enable signals, and up to two clear signals.
Table 6 on page 18 shows the sources that drive the peripheral bus and
how the IOC control signals share the peripheral bus.
Slew-Rate
Control
From Row or
Column FastTrack
Interconnect
4
2
8
13
To Row or
Column FastTrack
Interconnect
OE [7..0]
CLK [3..0]
ENA [5..0]
CLR [1..0]
Peripheral Control
Bus [12..0]
CLRN
DQ
ENA
VCC
6
VCC
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