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参数资料
| 型号： | EV-ADF4156SD1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4156 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4156 |
| 主要属性： | 单路分数-N PLL |
| 次要属性： | 6.2GHz |
| 已供物品： | 板，CD |
Data Sheet
ADF4156
Rev. E | Page 9 of 24
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic of the
phase frequency detector. The PFD includes a fixed-delay element
that sets the width of the antibacklash pulse, which is typically 3 ns.
This pulse ensures that there is no dead zone in the PFD transfer
function and results in a consistent reference spur level.
U3
CLR2
Q2
D2
U2
DOWN
UP
HI
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
05863-
008
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4156 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M4, M3, M2, and M1 (for details,
see Figure 16). Figure 15 shows the MUXOUT section in block
diagram form.
ANALOG LOCK DETECT
MUXOUT
DVDD
THREE-STATE OUTPUT
N-DIVIDER OUTPUT
DVDD
DGND
R-DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLOCK DIVIDER OUTPUT
R-DIVIDER/2
N-DIVIDER/2
CONTROL
05863-
009
MUX
Figure 15. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4156 digital section includes a 5-bit RF R-counter,
a 12-bit RF N-counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLOCK. The data is clocked in MSB first.
Data is transferred from the shift register to one of five latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. These bits are the three LSBs (DB2, DB1, and DB0), as
shown in Figure 2. The truth table for these bits is shown in
programmed.
PROGRAM MODES
program modes in the ADF4156.
Several settings in the ADF4156 are double buffered, including
the modulus value, phase value, R-counter value, reference doubler,
reference divide-by-2, and current setting. This means that two
events must occur before the part can use a new value for any of
the double buffered settings. The new value must first be latched
into the device by writing to the appropriate register, and then a
new write must be performed on Register R0. For example, after
the modulus value is updated, Register R0 must be written to in
order to ensure that the modulus value is loaded correctly.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
Register
0
Register R0
0
1
Register R1
0
1
0
Register R2
0
1
Register R3
1
0
Register R4
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| EV-ADF4157SD1Z | 功能描述:BOARD EVAL FOR ADF4157 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EV-ADF4159EB1Z | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADF4159 |
| EV-ADF4159EB2Z | 制造商:Analog Devices 功能描述:13GHZFRAC-NPLL+ADF55XXVCO+3VADM - Boxed Product (Development Kits) |
| EV-ADF4159EB3Z | 制造商:Analog Devices 功能描述:EVALUATIONBOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL BOARD FOR ADF4159 制造商:Analog Devices 功能描述:Clock & Timer Development Tools ADF4159 EVAL BRD |
| EV-ADF4360-0EB1Z | 功能描述:BOARD EVAL FOR ADF4360-0 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
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