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| 型号： | EVAL-AD5100EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5100 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | AD5100 |
| 主要属性： | 电压检测器和监控器 |
| 次要属性： | 开漏极输出 |
| 已供物品： | 板 |
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AD5100
OUTPUTS
SHUTDOWN OUTPUT, SHDN
The shutdown output, SHDN, is triggered by V 1MON or V 2MON
over- or underthreshold values, or as the result of a failed
watchdog input. SHDN can also be asserted low at any time
by writing to certain registers on the AD5100.
The shutdown generator asserts a logic low SHDN signal based
have formed across the SHDN pin and the battery terminal
(V 1MON ). The dendrite is blown immediately because M2a is
designed with adequate current sinking capability and remains
in the on position to offer such protection. In another situation,
if the SHDN pin is hard-shorted to the 12 V battery, the short-
circuit detector opens SW2 and limits the current by the high
impedance M2b.
on the following conditions:
?
During power-up
V 1MON
V REG
?
?
When V 2MON is below the turn-on threshold during the
rising edge or the turn-off threshold during the falling
#*
SW1
M1
LEVEL
SHIFTER
#
SW3
M3
?
?
When the external monitoring processor cannot issue
the necessary WDI signal and advanced WDI mode is
I 2 C? programmed shutdown
*
SW2
M2A
LOW-Z
M2B
HIGH-Z
R1
SHDN
To activate SHDN by writing to the part, the user must first
SHORT-CIRCUIT
enable this feature by writing to Register 0x18[4].
NOTES
DETECT
?
?
Register 0x18[4] = 0: enable software control of S HDN
Register 0x18[4] = 1: disable software control of SHDN
1. # = I 2 C SELECTABLE
2. * = DEFAULT
Figure 16. Shutdown Output
Once the feature is enabled, control of SHDN is achieved by
writing to Register 0x16[2].
RESET OUTPUT, RESET
The reset output, RESET, is triggered by V 3MON or V 4MON
?
?
Register 0x16[2] = 0: SHDN output not controlled by
software
Register 0x16[2] = 1: SHDN output is pulled low
underthreshold values. RESET activation can also be the result
of the processor not generating the proper watchdog signal, if
MR input is triggered, or if SHDN is activated.
The SHDN signal is released after the programmable hold time,
t SD_HOLD . The SHDN output is push-pull configured with an I 2 C-
The reset generator asserts the RESET signal based on the
following conditions:
selectable rail voltage of either V 1MON in default or internal V REG .
Register 0x0E[3] controls the voltage rail for SHDN. This bit
can be fixed in OTP memory.
?
?
?
During power-up
?
?
Register 0x0E[3] = 0: SHDN uses V 1MON rail (Default)
Register 0x0E[3] =1: SHDN uses V REG rail
?
When SHDN output is asserted (see Figure 7 and Figure 14 );
RESET follows SHDN hold and delay timings if triggered by
Resistor R1 ensures that SHDN is pulled to ground when the
AD5100 is not powered. When AD5100 is powered, M2a and
M2b are both on. M2a has relatively lower impedance than
?
?
the SHDN output
When the external monitoring processor cannot issue the
M2b and R1 so the SHDN remains low at shutdown. When
the AD5100 settles, SW1 is turned on. M1 is stronger than
M2a so SHDN is pulled to the rail, which takes AD5100 out
of the shutdown mode.
RESET is active low by default, but can be configured for active
high operation. Register 0x0D[1] controls the activation
polarity of RESET. It is possible to fix the value of this bit in
OTP memory.
In some applications, the AD5100 may monitor and control
power regulators where the input and enable pins are next to
?
?
Register 0x0D[1] = 0: RESET is active low (Default)
Register 0x0D[1] = 1: RESET is active high
each other in a fine pitch. This may pose reliability concerns
under some abnormal conditions. To prevent errors from happen-
ing, the AD5100 shutdown output features smart-load detection
to ensure that the shutdown responds. For example, if the car
battery has not started for a long time, a resistive dendrite may
Rev. A | Page 19 of 36
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