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参数资料
| 型号： | EVAL-AD5100EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5100 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | AD5100 |
| 主要属性： | 电压检测器和监控器 |
| 次要属性： | 开漏极输出 |
| 已供物品： | 板 |
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AD5100
Register
Read/
Permanently
NonOTP Power-On
Address
0x16
Write
R/W
Settable
No
Register Name and Bit Description
Special function 1
Default 1
0x00
Bit No.
[0]
[1]
[2]
[3]
[7:4]
Description
Reserved
Reserved
0: software assertion of SHDN pin is inactive
1: pulls SHDN pin low
0: override of permanent settings inactive
1: override of permanent settings active
Reserved
0x17
R/W
No
Special function 2
0x00
Bit No.
[0]
[7:1]
Description
0: software power-down of AD5100 inactive
1: software power-down of AD5100 active 2
Reserved
0x18
R/W
No
Disable special functions 3
0x00
Bit No.
[0]
[1]
[2]
[3]
[4]
[7:5]
Description
0: allows override of any of the registers in memory except
Register 0x16 Bit[2:0] and Register 0x17 Bit[0]
1: disables override of any of the registers in memory except
Register 0x16 Bit[2:0] and Register 0x17 Bit[0]
Reserved
Reserved
0: allows software power-down function
1: disables software power-down function
0: allows software assertion of SHDN pin
1: disables software assertion of SHDN pin
Reserved
0x19
Read-
No
Fault detect and status
0x40
only
(Bits[3:0] are level triggered bits that indicate the current state of the
comparators monitoring the V 1MON and V 2MON input pins; Bits[6:4] are edge
triggered fault detection bits that indicate what error conditions were present
when a SHDN event occurred)
Bit No.
[0]
[1]
[2]
[3]
[6:4]
[7]
Description
1 = V 2MON input < V 2MON off threshold
1 = V 2MON input > V 2MON on threshold
1 = V 1MON input < V 1MON UV threshold
1 = V 1MON input > V 1MON OV threshold
000: none
001: V 1MON UV only
010: V 1MON OV only
011: never occurred
100: V 2MON below off only (default)
101: V 1MON UV and V 2MON below off both occurred
110: V 1MON OV and V 2MON below off both occurred
111: never occurred
Reserved
1
2
3
Default settings of AD5100-0 evaluation model only.
V 2MON must be 0 V (that is, V 2MON must be configured in edge sensitive mode) for software power-down.
These register bits are set only. To clear them, the AD5100 must be power cycled. In some cases, the AD5100 can be connected to an I 2 C bus with lots of activity.
Setting these bits is an added means of ensuring that any erroneous activity on the bus does not cause AD5100 special functions to become active.
Rev. A | Page 25 of 36
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