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参数资料
| 型号： | EVAL-AD5290EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5290 |
| 设计资源： | AD5290 Evaluation Tools |
| 标准包装： | 1 |
| 主要目的： | 数字电位器 |
| 已用 IC / 零件： | AD5290 |
| 已供物品： | 板 |
| 相关产品： | AD5290YRMZ50-R7-ND - IC POT DGTL 50KW 256POS 10-MSOP AD5290YRMZ10-R7-ND - IC POT DGTL 10KW 256POS 10-MSOP AD5290YRMZ100-R7-ND - IC POT DGTL 100KW 256POS 10-MSOP AD5290YRMZ50-ND - IC DGTL POT 50K 256POS 10MSOP AD5290YRMZ100-ND - IC DGTL POT 100K 256POS 10MSOP AD5290YRMZ10-ND - IC DGTL POT 10K 256POS 10MSOP |
AD5290
Data Sheet
Rev. C | Page 18 of 20
APPLICATIONS
HIGH VOLTAGE DAC
AD5290 can be configured as a high voltage DAC, with out-
put voltage as high as 30 V. The circuit is shown in Figure 33.
The output is
)]
1
(
V
2
.
1
[
256
)
(
1
2
R
D
V
O
(4)
where D is the decimal code from 0 to 255.
AD5290
U2
OP284
V+
V–
OP284
VOUT
VDD
U1B
VDD
RBIAS
ADR512
D1
R2
R1
B
100k
0
4716
-01
8
U1A
Figure 33. High Voltage DAC
PROGRAMMABLE POWER SUPPLY
as the variable resistor at the regulator’s FB pin to provide the
programmable power supply (Figure 34). The output is
]
)
(
1
[
V
23
.
1
2
256
R
V
AB
D
O
(5)
a short, and VDD is one diode voltage drop below +5 V. The
output slowly establishes the final value.
AD5290
ADP1611
1.23V
CC
150pF
RC
220k
COUT
10
F
VOUT
D1
L1
4.7
H
IN
GND
SS
FB
RT
SW
COMP
U2
C1
0.1
F
VDD
R1
100k
A
W
B
CIN
10
F
5V
R2
8.5k
CSS
22nF
04716-
019
U1
Figure 34. Programmable Power Supply
AUDIO VOLUME CONTROL
Because of its good THD performance and high voltage
capability, AD5290 can be used as a digital volume control.
If AD5290 is used directly as an audio attenuator or gain
amplifier, a large step change in the volume level at any arbi-
trary time can lead to an abrupt discontinuity of the audio
signal causing an audible zipper noise. To prevent this, a zero-
crossing window detector can be inserted to the CS line to
delay the device update until the audio signal crosses the
window. Since the input signal can operate on top of any
dc level rather than absolute zero volt level, zero-crossing in
this case means the signal is ac-coupled, and the dc offset
level is the signal zero reference point.
The configuration to reduce zipper noise (Figure 35) and the
results of using this configuration are shown in Figure 36. The
input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B
The upper limit of the comparator is set above its offset and,
therefore, the output pulses high whenever the input falls
between 2.502 V and 2.497 V (or 0.005 V window) in this
example. This output is AND’ed with the chip select signal
such that the AD5290 updates whenever the signal crosses
the window. To avoid a constant update of the device, the
chip select signal should be programmed as two pulses, rather
than as one shown in Figure 36.
In Figure 35, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
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