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参数资料
| 型号： | EVAL-AD5290EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5290 |
| 设计资源： | AD5290 Evaluation Tools |
| 标准包装： | 1 |
| 主要目的： | 数字电位器 |
| 已用 IC / 零件： | AD5290 |
| 已供物品： | 板 |
| 相关产品： | AD5290YRMZ50-R7-ND - IC POT DGTL 50KW 256POS 10-MSOP AD5290YRMZ10-R7-ND - IC POT DGTL 10KW 256POS 10-MSOP AD5290YRMZ100-R7-ND - IC POT DGTL 100KW 256POS 10-MSOP AD5290YRMZ50-ND - IC DGTL POT 50K 256POS 10MSOP AD5290YRMZ100-ND - IC DGTL POT 100K 256POS 10MSOP AD5290YRMZ10-ND - IC DGTL POT 10K 256POS 10MSOP |
AD5290
Data Sheet
Rev. C | Page 16 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
VI
W
B
VO
04716-013
Figure 28. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B,
divided by the 256 positions of the potentiometer divider. The
general equation defining the output voltage at VW with respect
to ground for any valid input voltage applied to Terminal A and
Terminal B is
B
A
W
V
D
V
D
V
×
+
×
=
256
)
(
(3)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD5290 contains a 3-wire digital interface (CS, CLK,
and SDI). The 8-bit serial word must be loaded MSB first.
The format of the word is shown in Table 4. The positive edge
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic fami-
lies work well. When CS is low, the clock loads data into the
serial register on each positive clock edge.
The data setup and data hold times in the Specifications section
determine the valid timing requirements. The AD5290 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
DAISY CHAIN OPERATION
SDO shifts out the SDI content in the previous frame; thus it
can be used for daisy-chaining multiple devices. The SDO pin
contains an open drain N-Ch MOSFET and requires a pull-
up resistor if the SDO function is used. Users need to tie the
SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO to SDI interface
can induce time delay to the subsequent devices.
For example, in Figure 29, if two AD5290s are daisy-chained, a
total of 16 bits of data are required for each operation. The first
set of eight bits goes to U2, and the second set of eight bits goes
to U1. The CS should be kept low until all 16 bits are clocked
into their respective serial registers. The CS is then pulled high
to complete the operation.
AD5290
U1
SDO
SDI
CLK
CS
AD5290
U2
SDO
SDI
CLK
CS
C
+5V
RPU
2.2k
MOSI
SS
SCLK
04716-
014
Figure 29. Daisy Chain Configuration
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