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参数资料
| 型号： | EVAL-AD5290EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5290 |
| 设计资源： | AD5290 Evaluation Tools |
| 标准包装： | 1 |
| 主要目的： | 数字电位器 |
| 已用 IC / 零件： | AD5290 |
| 已供物品： | 板 |
| 相关产品： | AD5290YRMZ50-R7-ND - IC POT DGTL 50KW 256POS 10-MSOP AD5290YRMZ10-R7-ND - IC POT DGTL 10KW 256POS 10-MSOP AD5290YRMZ100-R7-ND - IC POT DGTL 100KW 256POS 10-MSOP AD5290YRMZ50-ND - IC DGTL POT 50K 256POS 10MSOP AD5290YRMZ100-ND - IC DGTL POT 100K 256POS 10MSOP AD5290YRMZ10-ND - IC DGTL POT 10K 256POS 10MSOP |
Data Sheet
AD5290
Rev. C | Page 17 of 20
ESD PROTECTION
All digital inputs are protected with a series input resistor and
a Zener ESD structure, as shown in Figure 30. These structures
apply to digital input pins, Pin CS, Pin CLK, Pin SDI, and
Pin SDO.
LOGIC
340
GND
04716-015
Figure 30. Equivalent ESD Protection Circuit
All analog terminals are also protected by Zener ESD protection
diodes, as shown in Figure 31.
VSS
VDD
A
W
B
04716-016
Figure 31. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
conditions for proper 3-terminal digital potentiometer opera-
tion. The AD5290 can operate in single supply from +4.5 V to
+33 V or dual supply from ±4.5 V to ±16.5 V. The AD5290 is
functional at low supply voltages such as 4.5 V, but the
performance parameters are not guaranteed.
The voltages present on Terminal A, Terminal B, and Terminal W
that are more positive than VDD or more negative than VSS are
clamped by the internal forward-biased diodes (Figure 31).
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W
any voltage to Terminal A, Terminal B, and Terminal W.
Otherwise, the diodes are forward-biased such that VDD/VSS
are powered unintentionally and affect the system. Similarly,
VDD/VSS should be powered down last. The ideal power-up
sequence is as follows: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA, VB, VW, and the digital
inputs is not important, as long as they are powered after
VDD/VSS.
LAYOUT AND POWER SUPPLY BIASING
It is good practice to use a compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR),
1 F to 10 F tantalum or electrolytic capacitors, should be
applied at the supplies to minimize any transient disturbance
and to filter low frequency ripple. Figure 32 illustrates the basic
supply-bypassing configuration for the AD5290.
The ground pin of the AD5290 is a digital ground reference.
To minimize the digital ground bounce, the AD5290 digital
ground terminal should be joined remotely to the analog
ground (Figure 32).
VDD
VSS
GND
C3
AD5290
C4
C1
+
C2
10
F
10
F
0.1
F
0.1
F
04716-017
Figure 32. Power Supply Bypassing
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