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参数资料
| 型号： | EVAL-AD5930EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5930 |
| 标准包装： | 1 |
| 主要目的： | 计时，波形发生器 |
| 已用 IC / 零件： | AD5930 |
| 次要属性： | 串行接口 |
| 已供物品： | 板，线缆 |
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Data Sheet
AD5930
Rev. | Page 21 of 28
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 1.
Note that if the part is only operating in continuous mode, then
Bit D7 in the control register should be set to 1.
3. External Increment, External Burst Control:
Both the increment interval (tINT) and the burst interval (TBURST)
are controlled by the CTRL pin. A 0 ≥ 1 transition on the CTRL
pin starts the sweep. The duration of CTRL high then dictates
the length of time the AD5930 bursts that frequency. The low
time of CTRL is the “listen” time, that is, how long the part
remains at midscale. Bringing the CTRL pin high again initiates a
frequency increment, and the pattern continues. For this mode,
the settings for Bit D13, Bit D12, and Bit D11 are ignored.
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the
control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 1, and INT/EXT INCR (Bit D5) must be set to 1.
Note that if the part is only operating in continuous mode, then
Bit D7 in the control register should be set to 1.
Interrupt Pin
This function is used as an interrupt during a frequency sweep.
A low-to-high transition on this pin is sampled by the internal
MCLK, thereby resetting internal state machines, which results
in the output going to midscale.
Standby Pin
Sections of the AD5930 that are not in use can be powered
down to minimize power consumption. This is done by using
the STANDBY pin. For the optimum power savings, it is
recommended to reset the AD5930 before entering standby,
because doing so reduces the power-down current to 20 A.
When this pin is high, the internal MCLK is disabled, and the
reference, DAC, and regulator are powered down. When in this
state, the DAC output of the AD5930 remains at its present
value as the NCO is no longer accumulating. When the device
is taken back out of standby mode, the MCLK is re-activated
and the sweep continues. To ensure correct operation for new
data, it is recommended that the device be internally reset using
a control register write or using the INTERRUPT pin, and then
restarted.
OUTPUTS FROM THE AD5930
The AD5930 offers a variety of outputs from the chip. The analog
outputs are available from the IOUT/IOUTB pins, and include a
sine wave and a triangle output. The digital outputs are available
from the MSBOUT pin and the SYNCOUT pin.
Analog Outputs
Sinusoidal Output
The SIN ROM is used to convert the phase information from
the frequency register into amplitude information, which results
in a sinusoidal signal at the output. To have a sinusoidal output
from the IOUT/IOUTB pins, set Bit SINE/TRI (Bit D9) to 1.
Triangle Output
The SIN ROM can be bypassed so that the truncated digital
output from the NCO is sent to the DAC. In this case, the
output is no longer sinusoidal. The DAC produces a 10-bit
linear triangular function. To have a triangle output from the
IOUT/IOUTB pins, set Bit SINE/TRI (D9) to 0. Note that the
DAC ENABLE bit (D10) must be 1 (that is, the DAC is enabled)
when using these pins.
VOUT MAX
3p/2
7p/2
p/2
5p/2
9p/2
11p/2
VOUT MIN
05333-
012
Figure 34. Triangle Output
Digital Outputs
Square Wave Output from MSBOUT
The inverse of the MSB from the NCO can be output from the
AD5930. By setting the MSBOUTEN (D8) control bit to 1, the
inverted MSB of the DAC data is available at the MSBOUT pin.
This is useful as a digital clock source.
DVDD
DGND
05333-
013
Figure 35. MSB Output
SYNCOUT Pin
The SYNCOUT pin can be used to give the status of the sweep.
It is user selectable for the end of the sweep, or to output a 4 ×
TCLOCK pulse at frequency increments. The timing information
for both of these modes is shown in Figure 6 and Figure 7.
The SYNCOUT pin must be enabled before use. This is done
using Bit D2 in the control register. The output available from
this pin is then controlled by Bit D3 in the control register. See
Table 5 for more information.
B
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