- 您现在的位置：买卖IC网 > PDF目录17048 > EVAL-AD7194EBZ (Analog Devices Inc)EVAL BOARD FOR AD7194 PDF资料下载
参数资料
| 型号： | EVAL-AD7194EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/57页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR AD7194 |
| 设计资源： | EVAL-AD7zzzEBZ Schematic AD7194 Gerber Files |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7194 |
| 已供物品： | 板，线缆 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
Data Sheet
AD7194
Rev. A | Page 39 of 56
DIGITAL FILTER
The AD7194 offers a lot of flexibility in the digital filter. The
device has five filter options. The device can be operated with
a sinc3 or sinc4 filter, chop can be enabled or disabled, and zero
latency can be enabled. Finally, an averaging block can be
included after the sinc filter, which gives a fast settling mode.
The option selected affects the output data rate, settling time,
and 50 Hz/60 Hz rejection. The following sections describe
each filter type, indicating the available output data rates for
each filter option. The filter response along with the settling
time and 50 Hz/60 Hz rejection is also discussed.
SINC4 FILTER (CHOP DISABLED)
When the AD7194 is powered up, the sinc4 filter is selected
by default and chop is disabled. This filter gives excellent noise
performance over the complete range of output data rates. It
also gives the best 50 Hz/60 Hz rejection, but it has a long
settling time.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
08566-
026
Figure 27. Sinc4 Filter (Chop Disabled)
Sinc4 Output Data Rate/Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time for the sinc4 filter is equal to
tSETTLE = 4/fADC
When a channel change occurs, the modulator and filter are
reset. The settling time is allowed to generate the first conver-
sion after the channel change. Subsequent conversions on this
channel occur at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
08566-
027
Figure 28. Sinc4 Channel Change
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input. Therefore, it continues to output conversions
at the programmed output data rate. However, it is at least four
conversions later before the output data accurately reflect the
analog input. If the step change occurs while the ADC is
processing a conversion, then the ADC takes five conversions
after the step change to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
08566-
028
Figure 29. Asynchronous Step Change in Analog Input
The 3 dB frequency for the sinc4 filter is equal to
f3dB = 0.23 × fADC
Table 28 gives some examples of the relationship between the
values in Bits FS[9:0] and the corresponding output data rate
and settling time.
Table 28. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
480
10
400
96
50
80
60
66.6
Sinc4 Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate.
The output data rate equals
fADC = 1/tSETTLE = fCLK/(4 × 1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
相关PDF资料 |
PDF描述 |
|---|---|
| ECC22DCMT-S288 | CONN EDGECARD 44POS .100 EXTEND |
| 0210490257 | CABLE JUMPER 1.25MM .051M 20POS |
| ADR445ARMZ-REEL7 | IC VREF SERIES PREC 5V 8-MSOP |
| RBC19DRYN-S13 | CONN EDGECARD 38POS .100 EXTEND |
| HKQ0603S0N7C-T | INDUCTOR HI FREQ 0.7NH 0201 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-AD7195EBZ | 功能描述:BOARD EVAL FOR AD7195 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-AD7262EDZ | 功能描述:BOARD EVAL CONTROL AD7262 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7264EDZ | 功能描述:BOARD EVALUATION FOR AD7264 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7265CB | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
| EVAL-AD7265CB1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
发布紧急采购，3分钟左右您将得到回复。