- 您现在的位置：买卖IC网 > PDF目录17050 > EVAL-AD7265EDZ (Analog Devices Inc)BOARD EVAL FOR AD7265 A/D CONV PDF资料下载
参数资料
| 型号： | EVAL-AD7265EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7265 A/D CONV |
| 标准包装： | 1 |
| ADC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 输入范围： | 0 ~ 5 V |
| 在以下条件下的电源（标准）： | 7mW @ 3V，17mW @ 5V |
| 工作温度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7265 |
| 已供物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
AD7265
Rev. A | Page 21 of 28
SCLK
DOUTA
DOUTB
INVALID DATA
VALID DATA
1
10
14
1
THE PART BEGINS
TO POWER UP.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
tPOWER-UP2
CS
04674-
033
Figure 38. Exiting Full Power-Down Mode
POWER-UP TIMES
As described in detail, the AD7265 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the DCAPA and DCAPB pins.
To power up from full power-down (whether using an internal
or external reference), approximately 1.5 ms should be allowed
Powering up from partial power-down requires much less time.
The power-up time from partial power-down is typically 1 μs;
however, if using the internal reference, then the AD7265 must
be in partial power-down for at least 67 μs in order for this
power-up time to apply.
When power supplies are first applied to the AD7265, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see Figure 34); in the second cycle, CS must be brought
high before the 10th SCLK edge but after the second SCLK
falling edge (see Figure 35). Alternatively, if it is intended to
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10
th SCLK falling
edge (see Figure 34); the second and third dummy cycles place
the part in full power-down (see Figure 37).
Once supplies are applied to the AD7265, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
POWER vs. THROUGHPUT RATE
The power consumption of the AD7265 varies with throughput
rate. When using very slow throughput rates and as fast an
SCLK frequency as possible, the various power-down options
can be used to make significant power savings. However, the
AD7265 quiescent current is low enough that even without
using the power-down options, there is a noticeable variation in
power consumption with sampling rate. This is true whether a
fixed SCLK value is used or if it is scaled with the sampling rate.
rate when operating in normal mode for a fixed maximum
SCLK frequency, and an SCLK frequency that scales with the
sampling rate with VDD = 3 V and VDD = 5 V, respectively. In all
cases, the internal reference was used.
04
67
4-
0
45
THROUGHPUT (kSPS)
1000
0
100
200
300
500
400
700
800
900
600
P
O
WE
R
(
m
W)
10.0
9.0
8.5
9.5
8.0
7.0
6.5
7.5
6.0
5.5
5.0
16MHz SCLK
VARIABLE SCLK
TA = 25°C
Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
04674-046
THROUGHPUT (kSPS)
1000
0
200
300
400
100
500
600
700
800
900
P
O
WE
R
(mW)
25
21
19
23
17
13
15
9
7
11
5
VARIABLE SCLK
TA = 25°C
16MHz SCLK
Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V
相关PDF资料 |
PDF描述 |
|---|---|
| GCM22DCSD | CONN EDGECARD 44POS DIP .156 SLD |
| MAX5258EVKIT+ | KIT EVAL FOR MAX5258 |
| MAX54XEVKIT# | BOARD EVAL DAC MAX541 MAX542 |
| GMA10DTKD | CONN EDGECARD 20POS DIP .125 SLD |
| REC5-053.3DRW/H2/A | CONV DC/DC 5W 4.5-9VIN +/-3.3V |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-AD7266CB | 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD I.C. - Bulk |
| EVAL-AD7266CB1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC |
| EVAL-AD7266CBZ | 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD I.C. - Bulk |
| EVAL-AD7266EDZ | 功能描述:BOARD EVAL FOR AD7266 A/D CONV RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| EVAL-AD7273CB | 制造商:Analog Devices 功能描述:Evaluation Board 3 MSPS,10-/12-Bit ADCs In 8-Lead TSOT 制造商:Analog Devices 功能描述:EVAL BD 3 MSPS,10-/12-BIT ADCS IN 8-LEAD TSOT - Bulk |
发布紧急采购，3分钟左右您将得到回复。