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| 型号： | EVAL-AD7265EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7265 A/D CONV |
| 标准包装： | 1 |
| ADC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 输入范围： | 0 ~ 5 V |
| 在以下条件下的电源（标准）： | 7mW @ 3V，17mW @ 5V |
| 工作温度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7265 |
| 已供物品： | 板 |
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AD7265
Rev. A | Page 13 of 28
THEORY OF OPERATION
When the ADC starts a conversion (see Figure 17), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V
CIRCUIT INFORMATION
The AD7265 is a fast, micropower, dual, 12-bit, single-supply,
ADC that operates from a 2.7 V to a 5.25 V supply. When
operated from either a 3 V or a 5 V supply, the AD7265 is
capable of throughput rates of 1 MSPS when provided with a
16 MHz clock.
The AD7265 contains two on-chip, differential track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. It is housed in a
32-lead LFCSP or a 32-lead TQFP, offering the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The analog input range for the part can be selected to be
a 0 V to V
and V
IN+
IN
pins must be matched;
otherwise, the two inputs will have different settling times,
resulting in errors.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VIN+
VIN–
VREF
04674-014
input or a 2 × V
REF
input, configured with either
single-ended or differential analog inputs. The AD7265 has an
on-chip 2.5 V reference that can be overdriven when an external
reference is preferred. If the internal reference is to be used
elsewhere in a system, then the output needs to be buffered first.
The AD7265 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the
Figure 17. ADC Conversion Phase
ANALOG INPUT STRUCTURE
Modes of Operation section.
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7265 in differential/pseudo differential
modes. In single-ended mode, V
CONVERTER OPERATION
The AD7265 has two successive approximation ADCs, each
based around two capacitive DACs.
IN
is internally tied to AGND.
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and starts conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
show simplified schematics of one of these ADCs in acquisition
and conversion phase, respectively. The ADC is comprised of
control logic, a SAR, and two capacitive DACs. In Figure 16 (the
acquisition phase), SW3 is closed, SW1 and SW2 are in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
The C1 capacitors in Figure 18 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors with a
capacitance of 45 pF typically.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VIN+
VIN–
VREF
04
67
4-
01
3
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins with optimum
values of 47 Ω and 10 pF. In applications where harmonic
distortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and may necessitate the use of an input buffer amplifier. The
choice of the op amp is a function of the particular application.
Figure 16. ADC Acquisition Phase
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