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| 型号： | EVAL-AD7466CBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7466 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行 |
| 输入范围： | 0 ~ 3.6 V |
| 在以下条件下的电源（标准）： | 0.9mW @ 100kSPS，3 V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7466 |
| 已供物品： | 板，CD |
| 相关产品： | AD7466BRTZREEL7DKR-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRTZ-R2-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRMZ-REEL7-ND - IC ADC 12BIT 1.6V LP 8-MSOP AD7466BRTZ-REEL-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRMZ-REEL-ND - IC ADC 12BIT 1.6V LP 8-MSOP AD7466BRTZREEL7CT-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRTZREEL7TR-ND - IC ADC 12BIT 1.6V LP SOT23-6 AD7466BRMZ-ND - IC ADC 12BIT 1.6V LP 8-MSOP AD7466BRT-R2CT-ND - IC ADC 12BIT 1.6V LP SOT23-6 |
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AD7466/AD7467/AD7468
Rev. C | Page 24 of 28
The connection diagram in Figure 33 shows how the ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode, and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC and, under certain conditions, equidistant sampling might
not be achieved.
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, there-
fore, the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given (that is, AX0 = TX0), the state of the SCLK is
checked. The DSP waits until the SCLK goes high, low, and high
again before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data can be transmitted, or it
can wait until the next clock edge.
For example, the ADSP-2181 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7466/
AD7467/
AD74681
SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY.
SDATA
ADSP-218x1
SCLK
DR
RFS
TFS
02643-034
CS
Figure 33. Interfacing to the ADSP-218x
AD7466/AD7467/AD7468 to DSP563xx Interface
The connection diagram in Figure 34 shows how the AD7466/
AD7467/AD7468 can be connected to the synchronous serial
interface (SSI) of the DSP563xx family of DSPs from Motorola.
The SSI is operated in synchronous mode and normal mode
(SYN = 1 and MOD = 0 in Control Register B, CRB) with an
internally generated word frame sync for both Tx and Rx
(Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Set the
word length in Control Register A (CRA) to 16 by setting Bits
WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word
length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0,
and WL0 = 1). This DSP does not offer the option for a 14-bit
word length, so the AD7467 word length is set up to 16 bits like
the AD7466 word length. In this case, the user should keep in
mind that the last two bits are invalid data because the SDATA
goes back into three-state on the 14th SCLK falling edge.
The frame sync polarity bit (FSP) in the CRB register can be set
to 1, which means the frame goes low and a conversion starts.
Likewise, by means of Bits SCD2, SCKD, and SHFD in the CRB
register, it is established that Pin SC2 (the frame sync signal)
and Pin SCK in the serial port are configured as outputs, and
the most significant bit (MSB) is shifted first. To summarize,
MOD = 0
SYN = 1
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0
For signal processing applications, it is imperative that the
frame synchronization signal from the DSP563xx provides
equidistant sampling.
AD7466/
AD7467/
AD74681
1ADDITIONAL PINS OMITTED FOR CLARITY.
DSP563xx1
SDATA
SRD
SCLK
SCK
SC2
02643-035
CS
Figure 34. Interfacing to the DSP563xx
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