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| 型号： | EVAL-AD7682EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD7682 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 12.5mW @ 250kSPS，5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7682 |
| 已供物品： | 板 |
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AD7682/AD7689
Data Sheet
Rev. D | Page 16 of 32
THEORY OF OPERATION
SW+
MSB
16,384C
INx+
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
INx– OR
COM
4C
2C
C
32,768C
SW–
MSB
16,384C
LSB
4C
2C
C
32,768C
07
35
3-
02
6
Figure 24. ADC Simplified Schematic
OVERVIEW
redistribution successive approximation register (SAR) analog-
to-digital converters (ADCs). These devices are capable of
converting 250,000 samples per second (250 kSPS) and power
down between conversions. For example, when operating with
an external reference at 1 kSPS, they consume 17 μW typically,
ideal for battery-powered applications.
multichannel, low power data acquisition system, including
16-bit SAR ADC with no missing codes
4-channel/8-channel, low crosstalk multiplexer
Internal low drift reference and buffer
Temperature sensor
Selectable one-pole filter
Channel sequencer
These components are configured through an SPI-compatible,
14-bit register. Conversion results, also SPI compatible, can be
read after or during conversions with the option for reading
back the configuration associated with the conversion.
and-hold and do not exhibit pipeline delay or latency.
be interfaced to any 1.8 V to 5 V digital logic family. They are
housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space
savings and allows flexible configurations. They are pin-for-pin
CONVERTER OPERATION
based on a charge redistribution DAC. Figure 24 shows the
simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary-weighted capacitors, which
are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW. All
independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the INx+ and INx (or COM)
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the INx+ and INx (or COM) inputs captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4, ... VREF/32,768). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
clock, the serial clock, SCK, is not required for the conversion
process.
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| EVAL-AD7683CB | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN |
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