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| 型号： | EVAL-AD7690SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7690 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 18 |
| 采样率（每秒）： | 400k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 17mW @ 100kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7690 |
| 已供物品： | 板 |
AD7690
Rev. B | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
VDD 2
IN+ 3
IN– 4
GND 5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
AD7690
TOP VIEW
(Not to Scale)
05792
-0
04
Figure 5. 10-Lead MSOP Pin Configuration
0
579
2-
0
05
1
REF
2
VDD
3
IN+
4
IN–
5
GND
10 VIO
9SDI
8SCK
7SDO
6CNV
TOP VIEW
(Not to Scale)
AD7690
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY OF
THE SOLDER JOINTS, IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO THE GROUND PLANE.
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 μF capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Differential Positive Analog Input.
4
IN
AI
Differential Negative Analog Input.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part, chain or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low. If SDI or CNV is low when the conversion is
complete, the busy indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
EPAD
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder
joints, it is recommended that the pad be soldered to the ground plane.
1AI = analog input, DI = digital input, DO = digital output, and P = power.
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