参数资料
型号: EVAL-AD7691SDZ
厂商: Analog Devices Inc
文件页数: 14/28页
文件大小: 0K
描述: BOARD EVAL FOR AD7691
标准包装: 1
系列: PulSAR®
ADC 的数量: 1
位数: 18
采样率(每秒): 250k
数据接口: 串行
输入范围: ±VREF
在以下条件下的电源(标准): 10.6mW @ 250kSPS,5 V
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7691
已供物品:
Data Sheet
AD7691
Rev. C | Page 21 of 28
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is normally used when a single AD7691 is connected
to an SPI-compatible digital host with an interrupt input, and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 41, and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7691
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge,
or SDI going high, whichever occurs first, SDO returns to high
impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
47k
CNV
SCK
SDO
SDI
AD7691
06
14
6-
01
7
Figure 41. 4-Wire CS Mode with Busy Indicator Connection Diagram
SDO
D17
D16
D1
D0
tDIS
SCK
1
2
3
171819
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
06
14
6-
01
8
Figure 42. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
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