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参数资料
| 型号： | EVAL-AD7691SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7691 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| ADC 的数量： | 1 |
| 位数： | 18 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行 |
| 输入范围： | ±VREF |
| 在以下条件下的电源（标准）： | 10.6mW @ 250kSPS，5 V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7691 |
| 已供物品： | 板 |
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Data Sheet
AD7691
Rev. C | Page 17 of 28
AD8031
AD7691
VIO
REF
VDD
10F
1F
10
10k
5V
1F
1
1OPTIONAL REFERENCE BUFFER AND FILTER.
06
14
6-
04
6
POWER SUPPLY
The AD7691 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and VDD. To reduce the
supplies needed, the VIO and VDD pins can be tied together. The
AD7691 is independent of power supply sequencing between VIO
and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.
The AD7691 powers down automatically at the end of each
conversion phase, and therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (as low as a few hertz) and low battery-powered applications.
Figure 34. Example of an Application Circuit
DIGITAL INTERFACE
Though the AD7691 has a reduced number of pins, it offers
flexibility in its serial interface modes.
1000
10
0.1
0.001
10
1M
SAMPLING RATE (SPS)
O
P
E
RAT
ING
C
URRE
NT
(
A
)
100
1k
100k
10k
VDD = 5V
VIO
06
14
6-
04
5
When in CS mode, the AD7691 is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin ADSP-BF53x or
ADSP-219x. In this mode, the AD7691 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
When in chain mode, the AD7691 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
Figure 33. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
For simplified applications, the AD7691, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 34. The reference line can be driven by
The system power supply directly.
A reference voltage with enough current output capability, such
as the ADR43x.
In either mode, the AD7691 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
A reference buffer, such as the AD8031, which can also filter the
system power supply, as shown in Figure 34.
The busy indicator feature is enabled
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see
and
).
In the chain mode if SCK is high during the CNV rising edge
(see Figure 46).
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