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参数资料
| 型号： | EVAL-AD7739EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7739 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 15.1k |
| 数据接口： | 串行 |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 85mW @ 5V |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7739 |
| 已供物品： | 板 |
| 相关产品： | AD7739BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRUZ-ND - IC ADC 24BIT 8-CH 24-TSSOP AD7739BRU-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRU-ND - IC ADC 24BIT 8-CH 24-TSSOP |
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Data Sheet
AD7739
Rev. A | Page 23 of 32
CONTINUOUS CONVERSION MODE
When the mode register is being written, the ADC status byte is
cleared and the RDY pin goes high, regardless of its previous
state. When the continuous conversion command is written to
the mode register, the ADC starts conversion on the channel
selected by the address of the mode register.
After the conversion is complete, the relevant channel data
register and channel status register are updated, the relevant
RDY bit in the ADC status register is set, and the AD7739
continues converting on the next enabled channel. The part
cycles through all enabled channels until put into another mode
or reset. The cycle period is the sum of all conversion times of
enabled channels, set by the corresponding channel conversion
time registers.
The RDY bit is reset when the relevant channel data register is
being read. The behavior of the RDY pin depends on the
RDYFN bit in the I/O port register. When the RDYFN bit is 0,
the RDY pin goes low when any channel has unread data. When
the RDYFN bit is set to 1, the RDY pin goes low only if all
enabled channels have unread data.
If an ADC conversion result is not read before a new ADC
conversion is completed, the new result overwrites the previous
one. The relevant RDY bit goes low and the RDY pin goes high
for at least 163 MCLK cycles (~26.5 s), indicating when the data
register is updated, and the previous conversion data is lost.
If the data register is being read as an ADC conversion completes,
the data register is not updated with the new result (to avoid
data corruption) and the new conversion data is lost.
Figure 18 shows the sequence of the digital interface signal for
the continuous conversion mode with Channels 0 and 1 enabled
and the RDYFN bit set to 0. The RDY pin goes low and the data
register is read after each conversion. Figure 19 shows a similar
sequence but with the RDYFN bit set to 1. The RDY pin goes
low and all data registers are read after all conversions are
completed. Figure 20 shows the RDY pin when no data is read
from the AD7739.
Figure 18. Continuous Conversion, CH0 and CH1, RDYFN = 0
Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 1
Figure 20. Continuous Conversion, CH0 and CH1, No Data Read
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
READ
DATA
CH1
CH1 CONVERSION
CH0 CONVERSION
READ
DATA
CH0
CH1 CONVERSION
READ
DATA
CH0
CH0 CONVERSION
READ
DATA
CH1
03742-0-019
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
READ
DATA
CH1
CH1 CONVERSION
CH0 CONVERSION
READ
DATA
CH0
CH1 CONVERSION
READ
DATA
CH0
CH0 CONVERSION
READ
DATA
CH1
03742-0-020
SERIAL
INTERFACE
START
CONTINUOUS
CONVERSION
RDY
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
03742-0-021
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