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参数资料
| 型号： | EVAL-AD7739EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7739 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 15.1k |
| 数据接口： | 串行 |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 85mW @ 5V |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7739 |
| 已供物品： | 板 |
| 相关产品： | AD7739BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRUZ-ND - IC ADC 24BIT 8-CH 24-TSSOP AD7739BRU-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRU-ND - IC ADC 24BIT 8-CH 24-TSSOP |
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Data Sheet
AD7739
Rev. A | Page 27 of 32
FREQUENCY RESPONSE
The Σ-Δ modulator runs at the MCLK frequency, which is
effectively the sampling frequency. Therefore, the modulator
Nyquist frequency is of the MCLK.
If chopping is enabled, the input signal is resampled by
chopping. Therefore, the overall frequency response features
notches close to the frequency of 1/channel conversion time.
The typical ADC frequency response plots are given in
Figure 25 and Figure 26. The plots are normalized to 1/channel
conversion time.
Note that these figures apply to each channel separately and are
based on individual channel conversion time. The signal is
effectively resampled once more in the multiplexer by switching
between enabled analog inputs.
Figure 25. Typical ADC Frequency Response, Chopping Enabled
Figure 26. Typical ADC Frequency Response, Chopping Disabled
EXTENDED VOLTAGE RANGE OF THE
ANALOG INPUT
The AD7739 output data code span corresponds to the nominal
input voltage range. The ADC is functional outside the nominal
input voltage range, but the performance might degrade. The
Σ-Δ modulator was designed to fully cover 16% analog input
overrange; outside this range, the performance might degrade
more rapidly.
When the clamp bit in the mode register is set to 1, the channel
data register is digitally clamped to either all 0s or all 1s when the
analog input voltage goes outside the nominal input voltage range.
As shown in Table 30 and Table 31, when clamp = 0, the data
reflects the analog input voltage outside the nominal voltage
range. In this case, the sign and OVR bits in the channel status
register must be considered along with the data register value to
decode the actual conversion result.
Note that the OVR bit in the channel status register is generated
digitally from the conversion result and indicates the Σ-Δ mod-
ulator (nominal) overrange. The OVR bit does not indicate
exceeding the absolute voltage limits of the AIN pin.
Table 30. Extended Input Voltage Range,
Nominal Voltage Range ±1.25 V, 16 Bits, Clamp = 0
Input (V)
Data (hex)
Sign
OVR
+1.45000
0x147B
0
1
+1.25008
0x0001
0
1
+1.25004
0x0000
0
1
+1.25000
0xFFFF
0
+0.00004
0x8001
0
0.00000
0x8000
0
0.00004
0x7FFF
1
0
1.25000
0x0000
1
0
1.25004
0xFFFF
1
1.25008
0xFFFE
1
1.45000
0xEB85
1
Table 31. Extended Input Voltage Range,
Nominal Voltage Range +1.25 V, 16 Bits, Clamp = 0
Input (V)
Data (hex)
Sign
OVR
+1.45000
0x28F5
0
1
+1.25004
0x0001
0
1
+1.25002
0x0000
0
1
+1.25000
0xFFFF
0
+0.00002
0x0001
0
+0.00000
0x0000
0
0.00002
0x0000
1
NORMALIZED INPUT FREQUENCY
(INPUT FREQUENCY
× CONVERSION TIME)
GAIN
(dB)
–120
–100
–80
–60
–40
–20
0
10
1
100
CHOP = 1
03742-0-026
NORMALIZED INPUT FREQUENCY
(INPUT FREQUENCY
× CONVERSION TIME)
GAIN
(dB)
–120
–100
–80
–60
–40
–20
0
10
1
100
CHOP = 0
03742-0-027
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