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参数资料
| 型号： | EVAL-AD7739EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7739 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 15.1k |
| 数据接口： | 串行 |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 85mW @ 5V |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7739 |
| 已供物品： | 板 |
| 相关产品： | AD7739BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRUZ-ND - IC ADC 24BIT 8-CH 24-TSSOP AD7739BRU-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRU-ND - IC ADC 24BIT 8-CH 24-TSSOP |
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AD7739
Data Sheet
Rev. A | Page 14 of 32
REGISTER ACCESS
The AD7739 is configurable through a series of registers. Some
of them configure and control general AD7739 features, while
others are specific to each channel. The register data widths
vary from 8 bits to 24 bits. All registers are accessed through the
communications register, that is, any communication to the
AD7739 must start with a write to the communications register
specifying which register is subsequently read or written.
COMMUNICATIONS REGISTER
8 Bits, Write-Only Register, Address 0x00
All communications to the part must start with a write operation to
the communications register (see Table 14 and Table 15). The
data written to the communications register determines whether
the subsequent operation is a read or write and to which register
this operation is directed. The digital interface defaults to expect
a write operation to the communications register after power-
on, after reset, or after the subsequent read or write operation to
the selected register is complete. If the interface sequence is lost,
the part can be reset by writing at least 32 serial clock cycles
with DIN high and CS low. (Note that all of the parts, including
the modulator, filter, interface, and all registers are reset in this
case.) Remember to keep DIN low while reading 32 bits or more
either in continuous read mode or with the dump bit and 24/16
bit in the mode register set.
Table 14. Communications Register Bits
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
0
R/W
6-bit register address
Table 15. Communications Register Bit Descriptions
Bit
Mnemonic
Description
7
0
This bit must be 0 for proper operation.
6
R/W
A 0 in this bit indicates that the next operation is a write to a specified register.
A 1 in this bit indicates that the next operation is a read from a specified register.
5 to 0
Address
These bits specify to which register the read or write operation is directed. For channel specific registers, the
three LSBs, that is, Bit 2, Bit 1, and Bit 0, specify the channel number. When the subsequent operation writes
to the mode register, the three LSBs specify the channel selected for the operation determined by the mode
register value. The analog inputs configuration depends on the COM1 and COM0 bits in the channel setup
register.
Bit 2
Bit 1
Bit 0
Channel
Single Input
Differential Input
0
AIN0 to AINCOM
AIN0 to AIN1
0
1
AIN1 to AINCOM
AIN2 to AIN3
0
1
0
2
AIN2 to AINCOM
AIN4 to AIN5
0
1
3
AIN3 to AINCOM
AIN6 to AIN7
1
0
4
AIN4 to AINCOM
AIN0 to AIN1
1
0
1
5
AIN5 to AINCOM
AIN2 to AIN3
1
0
6
AIN6 to AINCOM
AIN4 to AIN5
1
7
AIN7 to AINCOM
AIN6 to AIN7
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