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| 型号： | EVAL-ADAU1446EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频，音频处理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要属性： | 单芯片多通道 28/56 位音频 DSP |
| 次要属性： | I²C & SPI 接口 |
| 已供物品： | 板，软件 |
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ADAU1445/ADAU1446
Rev. A | Page 18 of 92
INITIALIZATION
Power-Up Sequence
The ADAU1445/ADAU1446 have a built-in initialization period,
which allows sufficient time for the PLL to lock and the registers
to initialize their values. On a positive edge of RESET, the PLL
settings are immediately set by the PLL0, PLL1, and PLL2 pins,
and the master clock signal is blocked from the chip subsystems.
The initialization time lasts 10 ms, which is measured from the
rising edge of RESET. New values should not be written via the
control port until the initialization is complete.
Table 6 shows some typical times to boot the ADAU1445/
ADAU1446 into the operational state necessary for an application,
assuming that a 400 kHz I2C clock or a 5 MHz SPI clock is used
and a full program, parameter set, and all registers (9 kB) are
loaded. In reality, most applications use less than this full amount,
and unused program and parameter RAM need not be initialized;
therefore, the total boot time may be shorter.
Recommended Program/Parameter Loading Procedure
When writing large amounts of data to the program or parameter
RAM in direct write mode, such as when downloading the initial
contents of the RAMs from an external memory, the processor core
should be disabled to prevent unpleasant noises from appearing
at the audio output. When small amounts of data are transmitted
during real-time operation of the DSP, such as when updating
individual parameters, the software safeload mechanism can be
used. More information is available in the Software Safeload section.
Power-Reduction Modes
Sections of the ADAU1445/ADAU1446 chips can be turned on
and off as needed to reduce power consumption. These include
the ASRCs, S/PDIF receiver and transmitter, auxiliary ADCs,
and DSP core. More information is available in the Master
Clock and PLL Modes and Settings section.
System Initialization Sequence
Before the IC can process audio in the DSP, the following initial-
ization sequence must be completed. (Step 5 through Step 11
can be performed in any order, as needed.)
1.
Power on the IC and bring it out of reset. The order of the
power supplies (DVDD, IOVDD, and AVDD) does not matter.
2.
Wait at least 10 ms for the initialization to complete.
3.
Enable the master clocks of all modules to be used (see the
Master Clock and PLL Modes and Settings section).
4.
Deassert the core run bit (see the DSP Core Modes and
Settings section).
5.
Set the serial input modes (see the Serial Input Port Modes
6.
Set the serial output modes (see the Serial Output Port
7.
Set the routing matrix modes (see details of Address 0xE080
to Address 0xE09B in the Flexible Audio Routing Matrix
Modes section).
8.
Set the DSP core rate select registers (see the DSP Core
Rate Select Register (Address 0xE220) section).
9.
Write the parameter RAM (Address 0x0000 to Address
0x0FFF).
10. Write the program RAM (Address 0x2000 to Address
0x2FFF).
11. Write all other necessary control registers, such as ASRCs
and S/PDIF (Address 0xE221 to Address 0xE24C).
12. Assert the core run bit (see the DSP Core Modes and
Settings section).
Table 6. Power-Up Time
PLL Lock Time (ms)
Approximate Boot Time; Loading Maximum Program/Parameter/Registers (ms)
Total (ms)
I2C (@ 400 kHz SCL)
SPI (@ 5 MHz CCLK)
SPI (@ 25 MHz CCLK)
10
25
2
0.4
10.4 to 35
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