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| 型号： | EVAL-ADAU1446EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/92页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1446 |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音频，音频处理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1446 |
| 主要属性： | 单芯片多通道 28/56 位音频 DSP |
| 次要属性： | I²C & SPI 接口 |
| 已供物品： | 板，软件 |
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ADAU1445/ADAU1446
Rev. A | Page 37 of 92
SERIAL INPUT PORT MODES AND SETTINGS
Each of the nine serial input ports is controlled by setting an
individual 2-byte word in the serial input mode register for each
port (see Table 23 for the register addresses). Each serial data
signal can be set to use any of the nine clock domains (slave
mode) or an internally generated LRCLK signal at fS,NORMAL,
fS,DUAL, or fS,QUAD. The default value for each serial port on reset is
set to stereo, I2S, 24-bit, negative LRCLK and BCLK polarity,
slave mode using a 50% duty cycle LRCLK (as opposed to a
synchronization pulse). This configuration corresponds to a
setting of 0x3C00. The serial data uses its corresponding clock
domain (that is, SDATA3 uses LRCLK3 and BCLK3).
Restrictions
When in MOST mode (packed TDM4 mode), the MSB position
of the serial data must be delayed by one bit clock from the start
of the frame (I2S position) and the data must be 16 bits wide
Each channel has a frame of 32 bits. Therefore, when in delay-
by-12 mode, the serial data can only be 16 or 20 bits wide (not
24 bits). When in delay-by-16 mode, the serial data can only be
16 bits wide.
Due to the limited maximum clock speed, master and slave modes
are only compatible with certain TDM modes. See Table 16 for
more details.
Serial Input Port Modes Registers (Address 0xE000 to
Address 0xE008)
Table 23. Addresses of Serial Input Port Modes Registers
Address
Name
Read/Write
Word Length
Decimal
Hex
57344
E000
Serial Input Port 0 modes
16 bits (2 bytes)
57345
E001
Serial Input Port 1 modes
16 bits (2 bytes)
57346
E002
Serial Input Port 2 modes
16 bits (2 bytes)
57347
E003
Serial Input Port 3 modes
16 bits (2 bytes)
57348
E004
Serial Input Port 4 modes
16 bits (2 bytes)
57349
E005
Serial Input Port 5 modes
16 bits (2 bytes)
57350
E006
Serial Input Port 6 modes
16 bits (2 bytes)
57351
E007
Serial Input Port 7 modes
16 bits (2 bytes)
57352
E008
Serial Input Port 8 modes
16 bits (2 bytes)
Table 24. Bit Descriptions of Serial Input Port Modes Registers
Bit Position
Description
Default
[15]
Clock output enable1
0
0 = LRCLK and BCLK output pins disabled
1 = LRCLK and BCLK output pins enabled
[14]
Frame sync type
0
0 = LRCLK 50/50 duty cycle clock signal (square wave)
1 = LRCLK synchronization pulse (narrow pulse)
[13:10]
Clock domain master/slave select1
Address specific2
0000 = slave to Clock Domain 0 (Port 1)
0001 = slave to Clock Domain 1 (Port 2)
0010 = slave to Clock Domain 2 (Port 3)
0011 = slave to Clock Domain 3 (Port 4)
0100 = slave to Clock Domain 4 (Port 5)
0101 = slave to Clock Domain 5 (Port 6
0110 = slave to Clock Domain 6 (Port 7)
0111 = slave to Clock Domain 7 (Port 8)
1000 = slave to Clock Domain 8 (Port 9)
1001 = master, clock is fS,NORMAL
1010 = master, clock is fS,DUAL
1011 = master, clock is fS,QUAD
[9]
Serial input BCLK polarity
0
0 = negative BCLK polarity
1 = positive BCLK polarity
[8]
Serial input LRCLK polarity
0
0 = negative BCLK polarity
1 = positive BCLK polarity
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