参数资料
| 型号： | EVAL-ADE7953EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADE7953 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7953 |
| 主要属性： | 3 通道 |
| 次要属性： | USB 接口 |
| 已供物品： | 2 板，CD |
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Data Sheet
INSTANTANEOUS POWERS AND WAVEFORM SAMPLING
ADE7953
The ADE7953 provides access to the current and voltage
channel waveform data, along with the instantaneous active,
reactive, and apparent powers. This information allows the
instantaneous data to be analyzed in more detail, including
reconstruction of the current and voltage input for harmonic
analyses. These measurements are available from a set of
Table 7. Waveform Sampling Registers
Measurement Register 24-Bit
Active power AWATT 0x212
(Current Channel A)
Active power BWATT 0x213
(Current Channel B)
Address
32-Bit
0x312
0x313
All measurements are updated at a rate of 6.99 kHz (CLKIN/512).
The ADE7953 provides an interrupt status bit, WSMP, that is
triggered at a rate of 6.99 kHz, allowing measurements to be
synchronized with the instantaneous signal update rate. This
status bit is available in the IRQSTATA register (Address 0x22D
and Address 0x32D). This signal can also be configured to
trigger an interrupt on the external IRQ pin by setting the
WSMP bit (Bit 17) in the IRQENA register (Address 0x22C
and Address 0x32C).
The ADE7953 also provides the option of issuing an unlatched,
data-ready signal at the same rate of 6.99 kHz. This signal provides
the same information as the WSMP interrupt, but it is unlatched
and, therefore, does not need to be serviced each time that new
Reactive power
(Current Channel A)
Reactive power
(Current Channel B)
Apparent power
(Current Channel A)
Apparent power
(Current Channel B)
Current
(Current Channel A)
Current
(Current Channel B)
Voltage
(voltage channel)
AVAR
BVAR
AVA
BVA
IA
IB
V
0x214
0x215
0x210
0x211
0x216
0x217
0x218
0x314
0x315
0x310
0x311
0x316
0x317
0x318
data is available. The data-ready signal goes high for a period of
280 ns before automatically returning low. The data-ready signal
is disabled by default and can be output on the REVP, ZX, and
ZX_I pins by setting the REVP_ALT, ZX_ALT, and ZXI_ALT
bits to 1001 in the ALT_OUTPUT register (Address 0x110).
Rev. B | Page 37 of 72
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