参数资料
| 型号： | EVAL-ADE7953EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADE7953 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7953 |
| 主要属性： | 3 通道 |
| 次要属性： | USB 接口 |
| 已供物品： | 2 板，CD |
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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADE7953
ZX 1
RESET 2
21 ZX_I
20 REVP
VINTD 3
DGND 4
IAP 5
IAN 6
PULL_HIGH 7
ADE7953
TOP VIEW
(Not to Scale)
19 CLKOUT
18 CLKIN
17 VDD
16 AGND
15 VINTA
NOTES
1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED
PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB
TO CONFER MECHANICAL STRENGTH TO THE PACKAGE.
CONNECT THE PAD TO AGND AND DGND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5, 6
7, 8
9, 10
11, 12
13
14
15
16
17
18
19
Mnemonic
ZX
RESET
VINTD
DGND
IAP, IAN
PULL_HIGH
IBP, IBN
VN, VP
REF
PULL_LOW
VINTA
AGND
VDD
CLKIN
CLKOUT
Description
Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can
be configured to output a range of alternative power quality signals (see the Alternative Output Functions
section).
Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for at minimum of 10 μs.
This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 μF capacitor in
parallel with a 100 nF ceramic capacitor.
Ground Reference for the Digital Circuitry.
Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated
with this input has a maximum gain stage of 22 (see the Analog Inputs section).
These pins should be connected to VDD for proper operation.
Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog
Inputs section).
Analog Input for Voltage Channel. This differential voltage input has a maximum input range of ±500 mV. The
PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section).
This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage
of 1.2 V. This pin should be decoupled with a 4.7 μF capacitor in parallel with a 100 nF ceramic capacitor.
Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the Reference Circuit
section).
This pin should be connected to AGND for proper operation.
This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 μF capacitor in
parallel with a 100 nF ceramic capacitor.
Ground Reference for the Analog Circuitry.
Power Supply (3.3 V) for the ADE7953 . For specified operation, the input to this pin should be within
3.3 V ± 10%. This pin should be decoupled with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor.
Master Clock Input for the ADE7953 . An external clock can be provided at this input. Alternatively, a parallel
resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the
ADE7953 . The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of
picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for
the load capacitance requirements.
Rev. B | Page 9 of 72
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