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| 型号： | EVAL-ADF4113EBZ1 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4113 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4113 |
| 主要属性： | 单路整数-N PLL |
| 次要属性： | 1.75GHz 图形用户界面 |
| 已供物品： | 板，线缆，软件 |
| 相关产品： | ADF4113BCPZ-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113HVBRUZ-RL7-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBRUZ-RL-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBCPZ-RL7-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113HVBCPZ-RL-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113HVBRUZ-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBCPZ-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113BRUZ-REEL7TR-ND - IC SYNTHESZR FREQ PLL RF 16TSSOP 更多... |
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Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 21 of 28
RESYNCHRONIZING THE PRESCALER OUTPUT
Table 7 (the Reference Counter Latch Map) shows two bits,
DB22 and DB21, which are labeled DLY and SYNC,
respectively. These bits affect the operation of the prescaler.
With SYNC = 1, the prescaler output is resynchronized with the
RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB
improvement is seen in the ADF4113. The lower bandwidth
devices can show an even greater improvement. For example,
the ADF4110 phase noise is typically improved by 3 dB when
SYNC is enabled.
With DLY = 1, the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler coincides with the
active edge on RF input; this causes the SYNC feature to break
down. It is important to be aware of this when using the SYNC
feature. Adding a delay to the RF signal, by programming
DLY = 1, extends the operating frequency and temperature
somewhat. Using the SYNC feature also increases the value of
the AIDD for the device. With a 900 MHz output, the ADF4113
AIDD increases by about 1.3 mA when SYNC is enabled and by
an additional 0.3 mA if DLY is enabled.
All the typical performance plots in this data sheet, except for
Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-
tion or delay enabled.
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| EVAL-ADF4113EBZ2 | 功能描述:BOARD EVAL FOR ADF4113 1750MHZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| EVAL-ADF4113HVEB1Z | 功能描述:BOARD EVALUATION FOR ADF4113HV RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADF4118EB1 | 制造商:AD 制造商全称:Analog Devices 功能描述:WCDMA Evaluation Board For PLL Frequency Synthesizer |
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