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| 型号： | EVAL-ADF4113EBZ1 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4113 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4113 |
| 主要属性： | 单路整数-N PLL |
| 次要属性： | 1.75GHz 图形用户界面 |
| 已供物品： | 板，线缆，软件 |
| 相关产品： | ADF4113BCPZ-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 20-LFCSP ADF4113HVBRUZ-RL7-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBRUZ-RL-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBCPZ-RL7-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113HVBCPZ-RL-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113HVBRUZ-ND - IC CHARGE PUMP HV SYNTH 16-TSSOP ADF4113HVBCPZ-ND - IC CHARGE PUMP HV SYNTH 20-LFCSP ADF4113BRUZ-REEL7TR-ND - IC SYNTHESZR FREQ PLL RF 16TSSOP 更多... |
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ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Rev. F | Page 22 of 28
APPLICATIONS
LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER
Figure 33 shows the ADF4111/ADF4112/ADF4113 being used
with a VCO to produce the LO for a GSM base station
transmitter.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 . A typical GSM system
would have a 13 MHz TCXO driving the reference input with-
out any 50 termination. In order to have channel spacing of
200 kHz (GSM standard), the reference input must be divided
by 65, using the on-chip reference divider of the ADF4111/
ADF4112/ADF4113.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter
component values, a number of items need to be considered. In
this example, the loop filter was designed so that the overall
phase margin for the system would be 45 degrees. Other PLL
system specifications are
KD = 5 mA
KV = 12 MHz/V
Loop Bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 33.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF out-
put terminal. A T-circuit configuration provides 50 matching
between the VCO output, the RF output, and the RFIN terminal
of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 33, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
ADF4111
ADF4112
ADF4113
CE
CLK
DATA
LE
1000pF
REFIN
100pF
CP
MUXOUT
CPGND
AGND
DGND
1nF
8.2nF
620pF
100pF
51
1
3.3k
5.6k
100pF
18
1TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50
.
2OPTIONAL MATCHING RESISTOR DEPENDING ON RFOUT FREQUENCY.
DECOUPLING CAPACITORS ON AVDD, DVDD, AND VP OF THE ADF411x
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
SPI
COMPATIBLE
SERIAL
BUS
RSET
RFINA
RFINB
AVDD DVDD VP
FREFIN
VDD
VP
LOCK
DETECT
VCC
VCO190-902T
18
18
100pF
RFOUT
4.7k
7
15
16
8
2
14
6
5
1
9
4
3
B
C
P
51
2
03496-0-038
Figure 33. Local Oscillator for GSM Base Station
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