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参数资料
| 型号： | EVAL-ADF4158EB1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADF4158 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4158 |
| 主要属性： | 单路分数-N PLL |
| 已供物品： | 板 |
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Data Sheet
ADF4158
Rev. G | Page 19 of 36
FUNCTION REGISTER (R3) MAP
With Register R3 DB[2:0] set to [0, 1, 1], the on-chip function
register is programmed as shown in Figure 26.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
N SEL
This setting is used to circumvent the issue of pipeline delay
between an update of the integer and fractional values in the
N-counter. Typically, the INT value is loaded first, followed by
the FRAC value. This can cause the N-counter value to be at an
incorrect value for a brief period of time equal to the pipeline
delay (about four PFD cycles). This has no effect if the INT value
has not been updated. However, if the INT value has been changed,
this can cause the PLL to overshoot in frequency while it tries to
lock to the temporarily incorrect N value. After the correct
fractional value is loaded, the PLL quickly locks to the correct
frequency. Introducing an additional delay to the loading of the
INT value using the N SEL bit causes the INT and FRAC values
to be loaded at the same time, preventing frequency overshoot.
The delay is turned on by setting Bit DB15 to 1.
SD Reset
For most applications, DB14 should be set to 0. When DB14 is
set to 0, the Σ-Δ modulator is reset on each write to Register R0.
If it is not required that the Σ-Δ modulator be reset on each
Register R0 write, set this bit to 1.
Ramp Mode
DB[11:10] determine the type of generated waveform.
PSK Enable
When DB9 is set to 1, PSK modulation is enabled. When set to
0, PSK modulation is disabled.
FSK Enable
When DB8 is set to 1, FSK modulation is enabled. When set to
0, FSK modulation is disabled.
Lock Detect Precision (LDP)
When DB7 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector (PD) Polarity
DB6 sets the phase detector polarity. When the VCO characteristics
are positive, set this bit to 1. When the VCO characteristics are
negative, set this bit to 0.
Power-Down
DB5 provides the programmable power-down mode. Setting
this bit to 1 performs a power-down. Setting this bit to 0 returns
the synthesizer to normal operation. While in software power-
down mode, the part retains all information in its registers.
Only when supplies are removed are the register contents lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load state
conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock-detect circuitry is reset.
5. The RFIN input is debiased.
6. The input register remains active and capable of loading
and latching data.
Charge Pump Three-State
DB4 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
Counter Reset
DB3 is the RF counter reset bit. When this bit is set to 1, the RF
synthesizer counters are held in reset. For normal operation, set
this bit to 0.
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