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| 型号： | EVAL-ADUC7024QSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/104页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC7024 |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 设计资源： | ADUC7024 Dev System Schematic/Brd Outline 7024 Gerber Files |
| 标准包装： | 1 |
| 系列： | QuickStart™ 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7024 |
| 所含物品： | 评估板、电源、缆线、软件和说明文档 |
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ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 12 of 104
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MCU CLOCK RATE
From 32 kHz Internal Oscillator
326
kHz
CD12 = 7
From 32 kHz External Crystal
41.78
MHz
CD12 = 0
Using an External Clock
0.05
44
MHz
TA = 85°C
0.05
41.78
MHz
TA = 125°C
START-UP TIME
Core clock = 41.78 MHz
At Power-On
130
ms
From Pause/Nap Mode
24
ns
CD12 = 0
3.06
s
CD12 = 7
From Sleep Mode
1.58
ms
From Stop Mode
1.7
ms
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
12
ns
From input pin to output pin
Element Propagation Delay
2.5
ns
POWER REQUIREMENTS13, 14
Power Supply Voltage Range
AVDD to AGND and IOVDD to IOGND
2.7
3.6
V
Analog Power Supply Currents
AVDD Current
200
A
ADC in idle mode; all parts except ADuC7019
400
A
ADC in idle mode; ADuC7019 only
3
25
A
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
7
10
mA
CD12 = 7
11
15
mA
CD12 = 3
40
45
mA
CD12 = 0 (41.78 MHz clock)
IOVDD Current in Pause Mode
25
30
mA
CD12 = 0 (41.78 MHz clock)
IOVDD Current in Sleep Mode
250
400
A
TA = 85°C
600
1000
A
TA = 125°C
Additional Power Supply Currents
ADC
2
mA
@ 1 MSPS
0.7
mA
@ 62.5 kSPS
DAC
700
A
per DAC
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed Up To
4
kV
FCIDM Passed Up To
0.5
kV
1
All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2
Apply to all ADC input channels.
3
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 59. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6
The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7
DAC linearity is calculated using a reduced code range of 100 to 3995.
8
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9
Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at 40°C, +25°C, +85°C, and +125°C.
10
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11
Test carried out with a maximum of eight I/Os set to a low output level.
12
See the POWCON register.
13
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14
IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15
On the ADuC7019/20/21/22, this current must be added to the AVDD current.
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