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| 型号： | EVAL-ADUC7128QSPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 83/92页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 产品培训模块： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 设计资源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 标准包装： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC7128 |
| 所含物品： | 评估板、电源、缆线、软件、仿真器和说明文档 |
| 产品目录页面： | 739 (CN2011-ZH PDF) |
| 相关产品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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ADuC7128/ADuC7129
Rev. 0 | Page 84 of 92
The XMxPAR are registers that define the protocol used for accessing the external memory for each memory region.
Table 121. XMxPAR MMR Bit Designations
Bit
Description
15
Enable Byte Write Strobe. This bit is only used for two,
8-bit memory sharing the same memory region.
Set by user to gate the AD0 output with the WS output. This allows byte write capability without using BHE and BLE signals.
Cleared by user to use BHE and BLE signals.
14:12
Number of Wait States on the Address Latch Enable Strobe.
11
Reserved.
10
Extra Address Hold Time.
Set by the user to disable extra hold time.
Cleared by the user to enable one clock cycle of hold on the address in read and write.
9
Extra Bus Transition Time on Read.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and after the read select (RS).
8
Extra Bus Transition Time on Write.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and after the write select (WS).
7:4
Number of Write Wait States. Select the number of wait states added to the length of the WS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock
cycles (default value).
3:0
Number of Read Wait States. Select the number of wait states added to the length of the RS pulse. 0x0 is 1 clock cycle; 0xF is 16 clock
cycles (default value).
TIMING DIAGRAMS
Figure 62 through Figure 65 show the timing for a read cycle (see Figure 62), a read cycle with address hold and bus turn cycles (see
Figure 63), a write cycle with address hold and write hold cycles (see Figure 64), and a write cycle with wait states (see Figure 65).
06
02
0-
06
9
HCLK
AD16:0
ADDRESS
DATA
MSx
AE
RS
Figure 62. External Memory Read Cycle
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相关代理商/技术参数 |
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|---|---|
| EVAL-ADUC7128QSPZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| EVAL-ADUC7129QSPZ | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-ADUC812QS | 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
| EVAL-ADUC812QSP | 制造商:AD 制造商全称:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
| EVAL-ADUC812QSZ | 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF) |
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