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| 型号： | EVAL-ADUC832QSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 54/92页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | QuickStart™ 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC832 |
| 所含物品： | 评估板，线缆，电源，软件和文档 |
| 其它名称： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 58 of 92
SERIAL PERIPHERAL INTERFACE
The ADuC832 integrates a complete hardware serial peripheral
interface (SPI) on chip. SPI is an industry standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, that is, full duplex. It
should be noted that the SPI pins are shared with the I2C pins.
Therefore, the user can only enable one or the other interface at
any given time (see SPE in Table 28). The SPI port can be confi-
gured for master or slave operation and typically consists of
four pins: MISO, MOSI, SCLOCK, and SS.
MISO (MASTER INPUT, SLAVE OUTPUT DATA PIN)
The MISO (master input, slave output) pin is configured as an
input line in master mode and an output line in slave mode.
The MISO line on the master (data in) should be connected to
the MISO line in the slave device (data out). The data is trans-
ferred as byte-wide (8-bit) serial data, MSB first.
MOSI (MASTER OUTPUT, SLAVE INPUT PIN)
The MOSI (master output, slave input) pin is configured as an
output line in master mode and an input line in slave mode.
The MOSI line on the master (data out) should be connected
to the MOSI line in the slave device (data in). The data is trans-
ferred as byte-wide (8-bit) serial data, MSB first.
SCLOCK (SERIAL CLOCK I/O PIN)
The master serial clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and
MISO data lines. A single data bit is transmitted and received in
each SCLOCK period. Therefore, a byte is transmitted/received
after eight SCLOCK periods. The SCLOCK pin is configured as
an output in master mode and as an input in slave mode. In
master mode, the bit rate, polarity, and phase of the clock are
controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the
SPICON SFR (see Table 28). In slave mode, the SPICON register
must be configured with the phase and polarity (CPHA and
CPOL) of the expected input clock. In both master and slave
modes, the data is transmitted on one edge of the SCLOCK
signal and sampled on the other. It is important therefore that
the CPHA and CPOL are configured the same for the master
and slave devices.
SS (SLAVE SELECT INPUT PIN)
The slave select (SS) input pin is shared with the ADC5 input.
To configure this pin as a digital input, the bit must be cleared,
for example, CLR P1.5.
This line is active low. Data is only received or transmitted in
slave mode when the SS pin is low, allowing the ADuC832 to be
used in single master, multislave SPI configurations. If CPHA = 1,
then the SS input may be permanently pulled low. With CPHA
= 0, the SS input must be driven low before the first bit in a
byte-wide transmission or reception, and return high again after
the last bit in that byte-wide transmission or reception. In SPI
slave mode, the logic level on the external SS pin can be read via
the SPR0 bit in the SPICON SFR.
The following SFR registers (SPICON and SPIDAT) are used to
control the SPI interface.
SPICON (SPI Control Register)
SFR Address:
F8H
Power-On Default Value:
04H
Bit Addressable:
Yes
Table 28. SPICON SFR Bit Designations
Bit
Name
Description
[7]
ISPI
SPI interrupt bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by
reading the SPIDAT SFR.
[6]
WCOL
Write collision error bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code.
[5]
SPE
SPI interface enable bit. Set by user to enable the SPI interface. Cleared by user to enable the I2C pins.
[4]
SPIM
SPI master/slave mode select bit. Set by user to enable Master Mode operation (SCLOCK is an output). Cleared by user to
enable slave mode operation (SCLOCK is an input).
[3]
CPOL1
Clock polarity select bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low.
[2]
CPHA1
Clock phase select bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to
transmit data.
[1:0]
SPR[1:0]
SPI bit rate select bits. These bits select the SCLOCK rate (bit rate) in master mode as follows:
SPR1
SPR0
Selected Bit Rate
0
fOSC/2
0
1
fOSC/4
1
0
fOSC/8
1
fOSC/16
In SPI slave mode, that is, SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit.
1
The CPOL and CPHA bits should both contain the same values for master and slave devices.
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