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| 型号： | EVAL-ADUC832QSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 89/92页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | QuickStart™ 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC832 |
| 所含物品： | 评估板，线缆，电源，软件和文档 |
| 其它名称： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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Data Sheet
ADuC832
Rev. B | Page 9 of 92
Parameter1
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
Power Supply Currents Power-Down Mode
Core_CLK = 2.097 MHz or 16.78 MHz
80
25
μA max
Oscillator on
38
14
μA typ
AVDD Current
2
1
μA typ
DVDD Current
35
20
μA max
Oscillator off
25
12
μA typ
Typical Additional Power Supply Currents
AVDD = DVDD = 5 V
PSM Peripheral
50
μA typ
ADC
1.5
mA typ
DAC
150
μA typ
1
Temperature range: 40°C to +125°C.
2
ADC linearity is guaranteed during normal MicroConverter core operation.
3
ADC LSB size = VREF/212, that is, for internal VREF = 2.5 V, 1 LSB = 610 V and for external VREF = 1 V, 1 LSB = 244 V.
4
Not production tested, but are guaranteed by design and/or characterization data on production release.
5
Offset error, gain error, offset error match, and gain error match are measured after factory calibration.
6
Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these
specifications.
7
SNR calculation includes distortion and noise components.
8
Channel-to-channel crosstalk is measured on adjacent channels.
9
The temperature sensor gives a measure of the die temperature directly; air temperature can be inferred from this result.
10
DAC linearity is calculated using:
Reduced code range of 100 to 4095, 0 V to VREF range.
Reduced code range of 100 to 3945, 0 V to VDD range.
DAC output load = 10 kΩ and 100 pF.
11
DAC differential nonlinearity specified on 0 V to VREF and 0 V to VDD ranges.
12
DAC specification for output impedance in the unbuffered case depends on DAC code.
13
DAC specifications for ISINK, voltage output settling time, and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in
unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
14
Measured with VREF and CREF pins decoupled with 0.1 F capacitors to ground. Power-up time for the internal reference is determined by the value of the decoupling
capacitor chosen for both the VREF and CREF pins.
15
When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1[6] bit. In this mode, the VREF and CREF pins
need to be shorted together for correct operation.
16
Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at 40°C, +25°C, and +125°C. Typical endurance at 25°C is 700,000 cycles.
18
Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature as shown in Figure 48 in the ADuC832 Flash/EE Memory Reliability section.
19
Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:
Normal mode: RESET = 0.4 V, digital I/O pins = open circuit, Core_CLK changed via the CD bits in PLLCON[2:0], core executing internal software loop.
Idle mode: RESET = 0.4 V, digital I/O pins = open circuit, Core_CLK changed via the CD bits in PLLCON, PCON[0] = 1, core execution suspended in idle mode.
Power-down mode: RESET = 0.4 V, all Port 0 pins = 0.4 V, all other digital I/O and Port 1 pins are open circuit, Core_CLK changed via the CD bits in PLLCON, PCON[1]
= 1, core execution suspended in power-down mode, oscillator turned on or off via OSC_PD bit (PLLCON[7]).
20
DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
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