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参数资料
| 型号： | FAN5069EMTCX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 11/22页 |
| 文件大小： | 622K |
| 描述： | IC REG DL BCK/LINEAR 16TSSOP |
| 产品变化通告： | Metallization Mask Rev 18/Apr/2007 |
| 标准包装： | 2,500 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 200kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | * |
| 包装： | 带卷 (TR) |
?2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5069 Rev. 1.1.5
11
PWM Operation
Refer to Figure 20 for the PWM control mechanism. The
FAN5069 uses the summing mode method of control to
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
generated ramp and the combined signal is amplified
and compared with the output of the error amplifier to get
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modu-
late the output of the summing block. The output of the
summing block is also compared against the voltage
threshold set by the R
LIM
resistor to limit the inductor cur-
rent on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility.
Initialization
When the PWM is disabled, the SW node is connected
to GND through an internal 500?MOSFET to slowly dis-
charge the output. As long as the PWM controller is
enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When V
CC
exceeds the UVLO threshold and EN is high,
the circuit releases SS and enables the PWM regulator.
The capacitor connected to the SS pin and GND is
charged by a 10礎 internal current source, causing the
voltage on the capacitor to rise. When this voltage
exceeds 1.2V, all protection circuits are enabled. When
this voltage exceeds 2.2V, the LDO output is enabled.
The input to the error amplifier at the non-inverting pin is
clamped by the voltage on the SS pin until it crosses the
reference voltage.
The time it takes the PWM output to reach regulation
(T
Rise
) is calculated using the following equation:
(C
SS
is in 糵)
(EQ. 2)
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an
external resistor, connected between R(T) pin and
ground. The frequency follows the graph, as shown in
Figure 18. The minimum clock frequency is 200KHz,
which is when R(T) pin is left open. Select the value of
R(T) as shown in the equation below. This equation is
valid for all F
OSC
> 200kHz.
(EQ. 3)
where F
OSC
is in Hz.
For example, for F
OSC
= 300kHz, R(T) = 50K?
R
RAMP
Selection and Feed-Forward Operation
The FAN5069 provides for input voltage feed-forward
compensation through R
RAMP
. The value of R
RAMP
effec-
tively changes the slope of the internal ramp, minimizing
the variation of the PWM modulator gain when input volt-
age varies. The R
RAMP
also has an effect on the current
limit, as can be seen in the R
LIM
equation (EQ. 5). The
R
RAMP
value can be approximated using the following
equation:
K?/DIV>
(EQ. 4)
where F
OSC
is in Hz. For example, for F
OSC
= 300kHz
and V
IN
= 12V, R
RAMP
540K?/SPAN>.
Gate Drive Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
and provides necessary amplification, level shifting, and
shoot-through protection. It also has functions that help
optimize the IC performance over a wide range of oper-
ating conditions. Since the MOSFET switching time can
vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than approxi-
mately 1V. Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET
has decreased to less than approximately 1V. This
allows a wide variety of upper and lower MOSFETs to be
used without a concern for simultaneous conduction, or
shoot-through.
A low impedance path between the driver pin and the
MOSFET gate is recommended for the adaptive dead-
time circuit to work properly. Any delay along this path
reduces the delay generated by the adaptive dead-time
circuit, thereby increasing the chances for shoot-through.
Protection
In the FAN5069, the converter is protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions. All of these conditions generate an
internal fault latch which shuts down the converter. For
all fault conditions both the high-side and the low-side
drives are off except in the case of OVP where the low-
side MOSFET is turned on until the voltage on the FB pin
goes below 0.4V. The fault latch can be reset either by
toggling the EN pin or recycling V
CC
to the chip.
Over Current Limit (PWM)
The PWM converter is protected against overloading
through a cycle-by-cycle current limit set by selecting
R
ILIM
resistor. An internal 10礎 current source sets the
threshold voltage for the output of the summing amplifier.
When the summing amplifier output exceeds this thresh-
old level, the current limit comparator trips and the PWM
starts skipping pulses. If the current limit tripping occurs
for 16 continuous clock cycles, a fault latch is set and the
controller shuts down the converter. This shutdown fea-
T
RISE
8 10
2
?/DIV>
C
SS
?/DIV>
=
R T
( )
5 10
9
?/DIV>
F
OSC
200 10
3
?/DIV>
(
)
------ ----------------- ----------------- ---------- -?/DIV>
=
R
RAMP
V
IN
1.8
6.3 10
8
"
Fosc
"
-------- ----------------- ----------------- ---
=
H
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