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参数资料
| 型号： | FAN5069EMTCX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 3/22页 |
| 文件大小： | 622K |
| 描述： | IC REG DL BCK/LINEAR 16TSSOP |
| 产品变化通告： | Metallization Mask Rev 18/Apr/2007 |
| 标准包装： | 2,500 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 200kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | * |
| 包装： | 带卷 (TR) |
?2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5069 Rev. 1.1.5
3
Pin Assignment
Figure 2. Pin Assignment
Pin Description
Pin #
Name
Description
1
FBLDO
LDO Feedback. This node is regulated to V
REF
.
2
R(T)
Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By plac-
ing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
3
ILIM
Current Limit. A resistor from this pin to GND sets the current limit.
4
SS
Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the
LDO during initialization. It also sets the time by which the converter delays when restarting
after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO
is enabled when SS reaches 2.2V.
5
COMP
COMP. The output of the error amplifier drives this pin.
6
FB
Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combi-
nation with the COMP pin, to compensate the feedback loop of the converter.
7
EN
Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a
latched fault condition. This is a CMOS input whose state is indeterminate if left open and
needs to be properly biased at all times.
8
AGND
Analog Ground. The signal ground for IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
9
SW
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and drain of low-side MOSFET.
10
HDRV
High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This
pin is also monitored by the adaptive shoot-through protection circuitry to determine when the
high-side MOSFET is turned off.
11
BOOT
Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver.
Connect to bootstrap capacitor as shown in Figure 1.
12
PGND
Power Ground. The return for the low-side MOSFET driver. Connect to the source of the low-
side MOSFET.
13
LDRV
Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin
is also monitored by the adaptive shoot-through protection circuitry to determine when the
lower MOSFET is turned off.
14
R(RAMP) Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
15
VCC
VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which draws current
when the input voltage is above 5.6V.
16
GLDO
Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.
FAN5069
16
15
14
13
12
11
10
9
GLDO
VCC
R(RAMP)
LDRV
PGND
BOOT
HDRV
SW
FBLDO
R(T )
ILIM
SS
COMP
FB
EN
AGND
1
2
3
4
5
6
7
8
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