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| 型号： | FDD3690 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V 22A D-PAK |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 标准包装： | 2,500 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 22A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 64 毫欧 @ 5.4A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 39nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 1514pF @ 50V |
| 功率 - 最大： | 1.6W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252 |
| 包装： | 带卷 (TR) |
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ
Max Units
Drain-Source Avalanche Ratings (Note 2)
W DSS
Single Pulse Drain-Source
V DD = 50 V,
I D = 5.4 A
175
mJ
Avalanche Energy
I AR
Maximum Drain-Source Avalanche
5.4
A
Current
Off Characteristics
BV DSS
Drain–Source Breakdown Voltage
V GS = 0 V,
I D = 250 μ A
100
V
? BV DSS
? T J
Breakdown Voltage Temperature
Coefficient
I D = 250 μ A, Referenced to 25 ° C
78
mV/ ° C
I DSS
I GSSF
I GSSR
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V DS = 80 V,
V GS = 20 V,
V GS = –20 V
V GS = 0 V
V DS = 0 V
V DS = 0 V
10
100
–100
μ A
nA
nA
On Characteristics
(Note 2)
V GS(th)
? V GS(th)
? T J
R DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain-Source
V DS = V GS , I D = 250 μ A
I D = 250 μ A, Referenced to 25 ° C
V GS = 10 V, I D = 5.4 A
2
2.4
–6.2
44
4
64
V
mV/ ° C
m ?
On-Resistance
V GS = 6 V, I D = 5.2 A
V GS = 10 V, I D = 5.4 A, T J = 125 ° C
47
88
71
135
I D(on)
On-State Drain Current
V GS = 10 V, V DS = 5 V
20
A
g FS
Forward Transconductance
V DS = 5 V,
I D = 5.4 A
20
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = 50 V,
f = 1.0 MHz
V GS = 0 V,
1514
82
44
pF
pF
pF
Switching Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
V DD = 50 V,
V GS = 10 V,
V DS = 50 V,
V GS = 10 V
I D = 1 A,
R GEN = 6 ?
I D = 5.4 A,
11
6.5
29
10
28
6.2
20
15
60
20
39
ns
ns
ns
ns
nC
nC
Q gd
Gate–Drain Charge
5.4
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
3.2
A
V SD
Drain–Source Diode Forward Voltage
V GS = 0 V,
I S = 3.2 A
(Note 2)
0.73
1.2
V
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
a) R θ JA = 40°C/W when mounted on a
1in 2 pad of 2 oz copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
P D
b) R θ JA = 96°C/W when mounted
on a minimum pad.
3. Maximum current is calculated as:
R DS(ON)
where P D is maximum power dissipation at T C = 25°C and R DS(on) is at T J(max) and V GS = 10V. Package current limitation is 21A
FDD3690 Rev. C(W)
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