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| 型号： | FDD86110 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V 12.5A DPAK-3 |
| 标准包装： | 2,500 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 12.5A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 10.2 毫欧 @ 12.5A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 35nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 2265pF @ 50V |
| 功率 - 最大： | 3.1W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252-3 |
| 包装： | 带卷 (TR) |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DSS
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 80 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
100
72
1
±100
V
mV/°C
μ A
nA
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
2
2.8
-10
4
V
mV/°C
V GS = 10 V, I D = 12.5 A
8.5
10.2
r DS(on)
Static Drain to Source On Resistance
V GS = 6 V, I D = 9.8 A
11.3
16
m Ω
V GS = 10 V, I D = 12.5 A,T J = 125°C
15
18
g FS
Forward Transconductance
V DS = 10 V, I D = 12.5 A
38
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 50 V, V GS = 0 V,
f = 1MHz
0.1
1702
379
17
0.5
2265
505
30
1.5
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
12
20
ns
t r
t d(off)
t f
Rise Time
Turn-Off Delay Time
Fall Time
V DD = 50 V, I D = 12.5 A,
V GS = 10 V, R GEN = 6 Ω
5.4
19
3.9
10
35
10
ns
ns
ns
Q g
Q gs
Q gd
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V GS = 0 V to 10 V
V DD = 50 V,
I D = 12.5 A
25
7.1
5.2
35
nC
nC
nC
Drain-Source Diode Characteristics
V SD
Source-Drain Diode Forward Voltage
V GS = 0 V, I S = 12.5 A
V GS = 0 V, I S = 2.6 A
(Note 2)
(Note 2)
0.80
0.72
1.3
1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = 12.5 A, di/dt = 100 A/ μ s
52
60
83
96
ns
nC
Notes :
1: R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
a) 40 °C/W when mounted on a
1 in 2 pad of 2 oz copper
b) 96 °C/W when mounted on
a minimum pad
2: Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3: Starting T J = 25 ° C, L = 0.3 mH, I AS = 30 A, V DD = 90 V, V GS = 10 V.
4: Pulsed Drain current is tested at 300 μ s with 2% duty cycle. For repetitive pulses, the pulse width is limited by the maximum junction temperature.
?2012 Fairchild Semiconductor Corporation
FDD86110 Rev.C3
2
www.fairchildsemi.com
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