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| 型号： | FDMF6706C |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 11/18页 |
| 文件大小： | 0K |
| 描述： | MODULE DRMOS 40A 1000KHZ 40PQFN |
| 标准包装： | 1 |
| 系列： | XS™ DrMOS |
| 类型： | 高端/低端驱动器 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 电流 - 输出 / 通道： | 40A |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-PowerTFQFN |
| 供应商设备封装： | 40-PQFN（6x6） |
| 包装： | 标准包装 |
| 其它名称： | FDMF6706CDKR |
Functional Description
The FDMF6706C is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1 MHz.
VCIN and Disable
The VCIN pin is monitored by an under-voltage lockout
(UVLO) circuit. When V CIN rises above ~3.1 V, the driver
is enabled for operation. When V CIN falls below ~2.7 V,
the driver is disabled (GH, GL=0). The driver can also
be disabled by pulling the DISB# pin LOW (DISB# <
V IL_DISB ), which holds both GL and GH LOW regardless
of the PWM input state. The driver can be enabled by
raising the DISB# pin voltage HIGH (DISB# > V IH_DISB ).
3-State PWM Input
The FDMF6706C incorporates a 3-state 5 V PWM input
gate drive design. The 3-state gate drive has both logic
HIGH level and LOW level, along with a 3-state
shutdown window. When the PWM input signal enters
and remains within the 3-state window for a defined
hold-off time (t D_HOLD-OFF ), both GL and GH are pulled
LOW. This feature enables the gate drive to shut down
both high-and low-side MOSFETs to support features
such as phase shedding, which is a common feature on
multiphase voltage regulators.
Operation when Exiting 3-State Condition
When exiting a valid 3-state condition, the FDMF6706C
design follows the PWM input command. If the PWM
Table 1.
UVLO and Disable Logic
input goes from 3-state to LOW, the low side MOSFET
is turned on. If the PWM input goes from 3-state to
UVLO
0
1
1
1
DISB#
X
0
1
Open
Driver State
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Enabled ( See Table 2 )
Disabled (GH, GL=0)
HIGH, the high-side MOSFET is turned on. This is
illustrated in Figure 21. The FDMF6706C design allows
for short propagation delays when exiting the 3-state
window ( see Electrical Characteristics ).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
Note:
3. DISB# has an internal pull-down current source of
10 μA.
Thermal Warning Flag
The FDMF6706C provides a thermal warning flag
(THWN) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN output
requires a pull-up resistor, which can be connected to
VCIN. THWN does NOT disable the DrMOS module.
referenced low R DS(ON) N-channel MOSFET. The bias
for GL is internally connected between VDRV and
CGND. When the driver is enabled, the driver's output is
180° out of phase with the PWM input. When the driver
is disabled (DISB#=0 V), GL is held LOW.
High-Side Driver
The high-side driver is designed to drive a floating N-
channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit,
consisting of the internal Schottky diode and external
bootstrap capacitor (C BOOT ). During startup, VSWH is
held at PGND, allowing C BOOT to charge to VDRV
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
Temperature
THWN
Logic
State
HIGH
135°C Reset 150°C
Activation
Temperature
Normal Thermal
Operation Warning
MOSFET (Q1). During this transition, the charge is
removed from C BOOT and delivered to the gate of Q1. As
Q1 turns on, V SWH rises to V IN , forcing the BOOT pin to
V IN + V BOOT , which provides sufficient V GS enhancement
for Q1. To complete the switching cycle, Q1 is turned off
by pulling GH to VSWH. C BOOT is then recharged to
VDRV when VSWH falls to PGND. GH output is in-
phase with the PWM input. The high-side gate is held
LOW
T J_driver IC
LOW when the driver is disabled or the PWM signal is
held within the 3-state window for longer than the 3-
state hold-off time, t D_HOLD-OFF .
Figure 20.
THWN Operation
? 2011 Fairchild Semiconductor Corporation
FDMF6706C ? Rev. 1.0.3
11
www.fairchildsemi.com
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