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| 型号： | FDMS3672 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V 7.4A POWER56-8 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品目录绘图： | Power56 Single |
| 标准包装： | 1 |
| 系列： | UltraFET™ |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 7.4A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 23 毫欧 @ 7.4A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 44nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 2680pF @ 50V |
| 功率 - 最大： | 2.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-MLP，Power56 |
| 供应商设备封装： | Power56 |
| 包装： | 标准包装 |
| 产品目录页面： | 1609 (CN2011-ZH PDF) |
| 其它名称： | FDMS3672DKR |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DS S
? T J
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
I D = 250 μ A, V GS = 0V
I D = 250 μ A, referenced to 25°C
100
104
V
mV/° C
I DSS
Zero Gate Voltage Drain Current
V DS = 80V,
V GS = 0V
T J = 55°C
1
10
μ A
I GSS
Gate to Source Leakage Current
V GS = ±20V, V DS = 0V
±100
nA
On Characteristics
V GS(th)
? V GS(th )
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25°C
2
3.1
-11
4
V
mV/°C
V GS = 10V, I D = 7.4A
19
23
r DS(on)
Drain to Source On Resistance
V GS = 6V, I D = 6.6A
24
29
m ?
V GS = 10V, I D = 7.4A, T J = 125°C
33
40
g FS
Forward Transconductance
V DS = 10V, I D = 7.4A
20
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 50V, V GS = 0V,
f = 1MHz
f = 1MHz
2015
210
90
1.3
2680
280
135
pF
pF
pF
?
Switching Characteristics
t d(on)
t r
t d(off)
t f
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
V DD = 50V, I D = 7.4A
V GS = 10V, R GEN = 6 ?
23
11
36
8
37
20
58
16
ns
ns
ns
ns
Q g
Q g
Q gs
Total Gate Charge at 10V
Total Gate Charge at 4.5V
Gate to Source Gate Charge
V GS = 0V to 10V
V GS = 0V to 4.5V
V DD = 50V
I D = 7.4A
31
9.5
44
nC
nC
nC
Q gd
Gate to Drain “Miller” Charge
8
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0V, I S = 7.4A
(Note 2)
0.8
1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = 7.4A, di/dt = 100A/ μ s
52
101
78
152
ns
nC
Notes:
1: R θ JA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a. 50°C/W when mounted on
a 1 in 2 pad of 2 oz copper
2: Pulse Test: Pulse Width < 30 0 μ s, Duty cycle < 2.0%.
b. 125°C/W when mounted on a
minimum pad of 2 oz copper
FDMS3672 Rev.C1
2
www.fairchildsemi.com
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