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| 型号： | FDMS6681Z |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 30V 21.1A POWER56 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Power 56 Pkg/Design Change 14/Apr/2009 |
| 产品目录绘图： | Power56 Single |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 30V |
| 电流 - 连续漏极(Id) @ 25° C： | 21.1A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 3.2 毫欧 @ 22.1A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 241nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 10380pF @ 15V |
| 功率 - 最大： | 2.5W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-PQFN，Power56 |
| 供应商设备封装： | Power56 |
| 包装： | 标准包装 |
| 产品目录页面： | 1609 (CN2011-ZH PDF) |
| 其它名称： | FDMS6681ZDKR |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
BV DSS
T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 A, V GS = 0 V
I D = -250 A, referenced to 25 °C
V DS = -24 V, V GS = 0 V
V GS = ±25 V, V DS = 0 V
-30
20
-1
±10
V
mV/°C
A
A
On Characteristics
V GS(th)
V GS(th)
T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 A
I D = -250 A, referenced to 25 °C
-1
-1.7
-7
-3
V
mV/°C
V GS = -10 V, I D = -22.1 A
2.7
3.2
r DS(on)
Static Drain to Source On Resistance
V GS = -4.5 V, I D = -15.7 A
4.0
5.0
m
V GS = -10 V, I D = -22.1 A, T J = 125 °C
3.9
5.0
g FS
Forward Transconductance
V DD = -10 V, I D = -22.1 A
143
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = -15 V, V GS = 0 V,
f = 1 MHz
7803
1540
1345
10380
2050
2020
pF
pF
pF
Switching Characteristics
t d(on)
Turn-On Delay Time
15
24
ns
t r
t d(off)
t f
Q g
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
V DD = -15 V, I D = -22.1 A,
V GS = -10 V, R GEN = 6
V GS = 0 V to -10 V
38
260
197
172
61
416
316
241
ns
ns
ns
nC
Q g
Q gs
Total Gate Charge
Gate to Source Charge
V GS = 0 V to -5 V
V DD = -15 V,
I D = -22.1 A
97
22
136
nC
nC
Q gd
Gate to Drain “Miller” Charge
46
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0 V, I S = -2.1 A
V GS = 0 V, I S = -22.1 A
(Note 2)
(Note 2)
0.68
0.79
1.2
1.25
V
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = -22.1 A, di/dt = 100 A/ s
44
39
71
63
ns
nC
NOTES:
1. R JA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
JC
is guaranteed by design while R
CA is
determined by
the user's board design.
a. 50 °C/W when mounted on
a 1 in 2 pad of 2 oz copper.
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%.
3. The diode connected between the gate and source servers only as protection against ESD. No gate overvoltage rating is implied.
?2009 Fairchild Semiconductor Corporation
FDMS6681Z Rev.C4
2
www.fairchildsemi.com
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