参数资料
型号: FDMS7572S
厂商: Fairchild Semiconductor
文件页数: 2/8页
文件大小: 0K
描述: MOSFET N-CH 25V 23A POWER56
标准包装: 1
系列: PowerTrench®, SyncFET™
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 25V
电流 - 连续漏极(Id) @ 25° C: 23A
开态Rds(最大)@ Id, Vgs @ 25° C: 2.9 毫欧 @ 23A,10V
Id 时的 Vgs(th)(最大): 3V @ 1mA
闸电荷(Qg) @ Vgs: 45nC @ 10V
输入电容 (Ciss) @ Vds: 2780pF @ 13V
功率 - 最大: 2.5W
安装类型: 表面贴装
封装/外壳: 8-PQFN,Power56
供应商设备封装: Power56
包装: 标准包装
其它名称: FDMS7572SDKR
Electrical Characteristics T A = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DSS
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current, Forward
I D = 1 mA, V GS = 0 V
I D = 10 mA, referenced to 25 °C
V DS = 20 V, V GS = 0 V
V GS = 20 V, V DS = 0 V
25
19
500
100
V
mV /° C
μ A
nA
On Characteristics (Note 2)
V GS(th)
? V GS(th)
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 1 mA
I D = 10 mA, referenced to 25 °C
1.2
1.7
-5
3.0
V
mV/°C
V GS = 10 V, I D = 23 A
2.4
2.9
r DS(on)
Static Drain to Source On Resistance
V GS = 4.5 V, I D = 18 A
3.4
4.2
m ?
V GS = 10 V, I D = 23 A, T J = 125 °C
3.5
4.3
g FS
Forward Transconductance
V DS = 5 V, I D = 23 A
159
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 13 V, V GS = 0 V,
f = 1 MHz
2090
577
128
1.1
2780
770
195
2.4
pF
pF
pF
?
Switching Characteristics
t d(on)
Turn-On Delay Time
10
20
ns
t r
t d(off)
t f
Q g
Q g
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V DD = 13 V, I D = 23 A,
V GS = 10 V, R GEN = 6 ?
V GS = 0 V to 10 V
V GS = 0 V to 4.5 V V DD = 13 V,
I D = 23 A
4
27
3
32
15
6.3
4.0
10
43
10
45
21
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0 V, I S = 2 A
V GS = 0 V, I S = 23 A
(Note 2)
(Note 2)
0.48
0.79
0.8
1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = 23 A, di/dt = 300 A/ μ s
23
17
36
31
ns
nC
Notes :
1. R θ JA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a. 50 °C/W when mounted on a
1 in 2 pad of 2 oz copper.
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 30 0 μ s, Duty cycle < 2.0%.
3. E AS of 84 mJ is based on starting T J = 25 ° C, L = 1 mH, I AS = 13 A, V DD = 23 V, V GS = 10 V. 100% test at L = 0.3 mH, I AS = 20 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
FDMS7572S Rev.C
2
www.fairchildsemi.com
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