参数资料
型号: FDN357N
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 小信号晶体管
英文描述: N-Channel Logic Level Enhancement Mode Field Effect Transistor
中文描述: 1900 mA, 30 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET
封装: SUPERSOT-3
文件页数: 2/4页
文件大小: 84K
代理商: FDN357N
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
BV
DSS
/
T
J
I
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, I
D
= 250 μA
I
D
= 250 μA, Referenced to 25
o
C
30
V
Breakdown Voltage Temp. Coefficient
36
mV/
o
C
Zero Gate Voltage Drain Current
V
DS
= 24 V, V
GS
= 0 V
1
μA
T
J
= 55°C
10
μA
I
GSSF
I
GSSR
ON CHARACTERISTICS
(Note)
Gate - Body Leakage, Forward
V
GS
= 20 V,V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
100
nA
Gate - Body Leakage, Reverse
-100
nA
V
GS(th)
V
GS(th)
/
T
J
R
DS(ON)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 μA
I
D
= 250 μA, Referenced to 25
o
C
1
1.6
2
V
Gate Threshold Voltage Temp. Coefficient
-3.6
mV/
o
C
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 1.9 A
0.081
0.09
T
J
=125°C
0.11
0.14
V
GS
= 10 V, I
D
= 2.2 A
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 5 V, I
D
= 1.9 A
0.053
0.06
I
D(ON)
g
FS
DYNAMIC CHARACTERISTICS
On-State Drain Current
5
A
Forward Transconductance
5
S
C
iss
C
oss
C
rss
SWITCHING CHARACTERISTICS
(Note)
Input Capacitance
V
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
235
pF
Output Capacitance
145
pF
Reverse Transfer Capacitance
50
pF
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Turn - On Delay Time
V
DD
= 10 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
5
10
ns
Turn - On Rise Time
12
22
ns
Turn - Off Delay Time
12
22
ns
Turn - Off Fall Time
3
8
ns
Total Gate Charge
V
DS
= 10 V, I
D
= 1.9 A,
V
GS
= 5 V
4.2
5.9
nC
Gate-Source Charge
1.3
nC
Gate-Drain Charge
1.7
nC
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current
0.42
A
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.42 A
(Note)
0.71
1.2
V
Note:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment :
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%.
FDN357N Rev.C
a. 250
a 0.02 in
o
C/W when mounted on
2
pad of 2oz Cu.
b. 270
o
C/W when mounted on
a 0.001 in
2
pad of 2oz Cu.
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