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| 型号： | FDS6892A |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH DUAL 20V 7.5A 8SOIC |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 |
| 产品目录绘图： | Power MOSFET, 8-SOP, SO-8 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | 2 个 N 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 7.5A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 18 毫欧 @ 7.5A，4.5V |
| Id 时的 Vgs(th)（最大）： | 1.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 17nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 1333pF @ 10V |
| 功率 - 最大： | 900mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 标准包装 |
| 产品目录页面： | 1603 (CN2011-ZH PDF) |
| 其它名称： | FDS6892ADKR |
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Off Characteristics
BV DSS
Drain–Source Breakdown Voltage
V GS = 0 V,
I D = 250 μ A
20
V
? BV DSS
? T J
I DSS
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
I D = 250 μ A, Referenced to 25 ° C
V DS = 16 V, V GS = 0 V
V DS = 16 V, V GS = 0 V, T J = 55 ° C
5
1
10
mV/ ° C
μ A
I GSSF
Gate–Body Leakage, Forward
V GS = 12 V,
V DS = 0 V
100
nA
I GSSR
Gate–Body Leakage, Reverse
V GS = –12 V, V DS = 0 V
–100
nA
On Characteristics
(Note 2)
V GS(th)
Gate Threshold Voltage
V DS = V GS ,
I D = 250 μ A
0.6
0.9
1.5
V
? V GS(th)
? T J
Gate Threshold Voltage
Temperature Coefficient
I D = 250 μ A, Referenced to 25 ° C
–3
mV/ ° C
R DS(on)
Static Drain–Source
V GS = 4.5 V,
I D = 7.5 A
13
18
m ?
On–Resistance
V GS = 2.5 V, I D = 6.5 A
V GS = 4.5 V,I D = 7.5 A,T J = 125 ° C
17
18
24
27
I D(on)
g FS
On–State Drain Current
Forward Transconductance
V GS = 4.5V,
V DS = 5 V,
V DS = 5 V
I D = 7.5 A
15
37
A
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = 10 V,
f = 1.0 MHz
V GS = 0 V,
1333
301
160
pF
pF
pF
Switching Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
V DD = 10 V,
V GS = 4.5 V,
V DS = 10 V,
V GS = 4.5 V
I D = 1 A,
R GEN = 6 ?
I D = 7.5 A,
8
15
26
9
12
2.5
16
27
42
18
17
ns
ns
ns
ns
nC
nC
Q gd
Gate–Drain Charge
3
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
1.3
A
V SD
Drain–Source Diode Forward
V GS = 0 V,
I S = 1.3 A
(Note 2)
0.7
1.2
V
Voltage
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
in pad of 2 oz
a) 78°C/W when
mounted on a 0.5in
pad of 2 oz copper
2
b) 125°C/W when
mounted on a 0.02
2
c) 135°C/W when mounted on a
minimum mounting pad.
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
FDS6892A Rev C (W)
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