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参数资料
| 型号： | FDS7079ZN3 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | JFETs |
| 英文描述： | TV 29C 29#16 SKT RECP |
| 中文描述： | 16 A, 30 V, 0.0075 ohm, P-CHANNEL, Si, POWER, MOSFET |
| 封装： | FLMP, SO-8 |
| 文件页数： | 2/6页 |
| 文件大小： | 183K |
| 代理商： | FDS7079ZN3 |
FDS7079ZN3 Rev C1 (W)
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ Max Units
Off Characteristics
BV
DSS
BV
DSS
T
J
I
DSS
I
GSS
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
V
GS
= 0 V,
I
D
= –250
μ
A,Referenced to 25
°
C
V
DS
= –24 V, V
GS
= 0 V
V
GS
= ±25 V, V
DS
= 0 V
I
D
= –250
μ
A
–30
V
–20
mV/
°
C
μ
A
μ
A
–1
±10
On Characteristics
V
GS(th)
V
GS(th)
T
J
R
DS(on)
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
V
DS
= V
GS
,
I
D
= –250
μ
A,Referenced to 25
°
C
V
GS
= –10 V, I
D
= –16 A
V
GS
= –4.5 V, I
D
= –13 A
V
GS
= –10 V, I
D
=–16A, T
J
=125
°
C
V
DS
= –10 V, I
D
= –16 A
I
D
= –250
μ
A
–1
–1.5
–3
V
0.5
mV/
°
C
m
6.7
9.4
9.2
47
7.5
11.5
g
FS
Forward Transconductance
S
Dynamic Characteristics
C
iss
Input Capacitance
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
R
G
Gate Resistance
3630
985
490
3.0
pF
pF
pF
V
DS
= –15 V, V
GS
= 0 V,
f = 1.0 MHz
V
GS
= 15 mV, f = 1.0 MHz
Switching Characteristics
(Note 2)
t
d(on)
Turn–On Delay Time
t
r
Turn–On Rise Time
t
d(off)
Turn–Off Delay Time
t
f
Turn–Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate–Source Charge
Q
gd
Gate–Drain Charge
10
20
64
98
39
10
15
19
35
102
157
55
ns
ns
ns
ns
nC
nC
nC
V
DD
= –15 V, I
D
= –1 A,
V
GS
= –10 V, R
GEN
= 6
V
DS
= –15 V, I
D
= –16 A,
V
GS
= –5 V
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
t
RR
Reverse Recovery Time
Q
RR
Reverse Recovery Charge
–2.5
A
V
SD
V
GS
= 0 V,
I
S
= –2.5 A
(Note 2)
–0.7
–1.2
V
38
24
ns
nC
I
F
= –16 A,
d
iF
/d
t
= 100 A/μs
(Note 2)
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a)
40°C/W when
mounted on a 1in
2
pad
of 2 oz copper
b)
85°C/W when mounted on
a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3.
The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
F
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