参数资料
型号: FDT86113LZ
厂商: Fairchild Semiconductor
文件页数: 2/6页
文件大小: 0K
描述: MOSFET N-CH 100V DUAL LL SOT-223
标准包装: 4,000
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 100V
电流 - 连续漏极(Id) @ 25° C: 3.3A
开态Rds(最大)@ Id, Vgs @ 25° C: 100 毫欧 @ 3.3A,10V
Id 时的 Vgs(th)(最大): 2.5V @ 250µA
闸电荷(Qg) @ Vgs: 6.8nC @ 10V
输入电容 (Ciss) @ Vds: 315pF @ 50V
功率 - 最大: 2.2W
安装类型: 表面贴装
封装/外壳: TO-261-4,TO-261AA
供应商设备封装: SOT-223
包装: 带卷 (TR)
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
' BV DSS
' T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 P A, V GS = 0 V
I D = 250 P A, referenced to 25 °C
V DS = 80 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
100
71
1
±10
V
mV/°C
P A
P A
On Characteristics (Note 2)
V GS(th)
' V GS(th)
' T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 P A
I D = 250 P A, referenced to 25 °C
1.0
1.7
-5
2.5
V
mV/°C
V GS = 10 V, I D = 3.3 A
75
100
r DS(on)
g FS
Static Drain to Source On Resistance
Forward Transconductance
V GS = 4.5 V, I D = 2.7 A
V GS = 10 V, I D = 3.3 A,
T J = 125 °C
V DS = 10 V, I D = 3.3 A
95
140
8
145
189
m :
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = 50 V, V GS = 0 V,
f = 1 MHz
234
46
3.1
315
65
5
pF
pF
pF
Switching Characteristics
t d(on)
Turn-On Delay Time
3.8
10
ns
t r
t d(off)
t f
Q g
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
V DD = 50 V, I D = 3.3 A,
V GS = 10 V, R GEN = 6 :
V GS = 0 V to 10 V
1.3
10
1.5
4.1
10
20
10
6.8
ns
ns
ns
nC
Q g
Q gs
Total Gate Charge
Gate to Source Gate Charge
V GS = 0 V to 5 V
V DD = 50 V,
I D = 3.3 A
2.3
0.68
3.9
nC
nC
Q gd
Gate to Drain “Miller” Charge
0.85
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0 V, I S = 3.3 A
V GS = 0 V, I S = 1 A
(Note 2)
(Note 2)
0.86
0.77
1.3
1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = 3.3 A, di/dt = 100 A/ P s
31
21
49
34
ns
nC
Notes :
1. R T JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R T JC is guaranteed by design while R T JA is determined by the user’s board design.
a) 55 °C/W when mounted on a
1 in 2 pad of 2 oz copper
b) 118 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 P s, Duty cycle < 2.0%.
3. Starting T J = 25 ° C, L = 0.3 mH, I AS = 8 A, V DD = 90 V, V GS = 10 V.
4. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
FDT86113LZ Rev.C
2
www.fairchildsemi.com
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