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参数资料
| 型号： | FMS2704LT1C |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封装： | TSSOP-24 |
| 文件页数： | 18/39页 |
| 文件大小： | 173K |
| 代理商： | FMS2704LT1C |
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FMS2704/FMS2704L
PRODUCT SPECIFICATION
REV. 1.01 12/2/99
25
Preceding each slave write, there must be a start cycle. Follow-
ing the pointer byte there should be a stop cycle. After the last
read, there must be a stop cycle comprising a LOW-to-HIGH
transition of SDA while SCL is HIGH. (see Figure 8, right
waveform)
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without rst gener-
ating a stop signal to terminate the current communication.
This is used to change the mode of communication (read,
write) between the slave and master without releasing the
serial interface lines.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles. For
sequential register accesses, each ACK handshake initiates
further SCL clock cycles from the master to transfer the next
data byte.
Write to one control register
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte
4.
Data byte to base address
5.
Stop signal
Read from one control register
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte (= base address)
4.
Stop signal
5.
Start signal
6.
Slave Address byte (R/W bit = HIGH)
7.
Data byte from base address
8.
Stop signal
Registers
Based upon setup commands via the Serial Bus, the FMS2704
gathers sensor inputs from the Tachometers, Thermometers and
Voltmeters. Measured values are compared against reference
values stored in the Trip and Limit registers. Fault conditions
set ags in the Interrupt registers and activate THERM and
INT outputs. Sensor and interrupt status are passed to the host
via the Serial Bus interface. Host commands set the FMS2704
conguration, interrupt masking and the fan speed.
Following power-up, registers are set to default values. After a
200 msec. power up reset delay, the FMS2704 will begin
checking sensor inputs to determine if the temperature in volt-
ages fall within default limits, which can be overridden by
changing the values stored in the Value RAM.
If the PTL7-0 and PTR7-0 values are changed, then the
TRIP_LOCK (Temperature Trip Point Lock) bit in the Cong-
uration Register must be set to enable temperature values to be
compared against the programmable rather than the xed trip
point values. If the temperature limit values are changed, then
the changes are effective immediately. Interrupt masking (reg-
ister 0x43), enabling (INT_EN bit) and clearing (INT_CLR
bit) can be used to disable interrupts during register setup.
Register functions and bit assignments dened in the Address-
able Memory and Global Register Denitions sections.
Temperature register outputs, TR7-0 and TA7-0 are compared
with the limit values TRHI7-0, TRLO7-0, TAHI7-0 and TALO7-0
that are stored in the Limit Registers. Out of range TA7-0 and
TR7-0 values set the INT bit in the Interrupt Status Register.
TR7-0 and TA7-0 are also compared with the values in Trip
Point Registers, PTL7-0 and PTR7-0 if these registers have
been loaded or FTL7-0 and FTR7-0, which contain power up
default values.
Fan Speed Outputs
Fan speed outputs FAN_SPDA and FAN_SPDB can be pro-
grammed individually to be either 0–2.5V analog output or
Pulse Width Modulated Output. Register values are set
directly through the Serial Bus by external software or rm-
ware following interrogation to temperature and tachometer
values. Also, the fan speed may be derived from the internal
registers, SPEEDA and SPEEDB or from the Channel A or
Channel B Fan Speed Controllers.
If the A Channel analog output is selected, the output of the
ADAC D/A converter is connected to the FAN_SPDA output.
If A Channel PWM is selected, then Pulse Width Modulator is
connected to the FAN_SPDA output. B channel analog/PWM
selection functions similarly.
Reset Generator
The Reset Generator emits a RST = L pulse under either of the
following conditions:
1.
STANDBY = L, causing no internal reset, INTRST.
2.
VCCA & VCCD < 4.4V (FMS2704) or
VCCA & VCCD < 2.9V (FMS2704L),
Following release of the reset stimulus, RST = L for a further
200 msec.
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