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参数资料
| 型号： | FUSB2805MLX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 5/49页 |
| 文件大小： | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
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Protocol Description
ULPI References
The FUSB2805 provides a 12-pin (SDR) ULPI interface
for communication with the link controller. It is strongly
recommended that users of the FUSB2805 read the
ULPI and UTMI+ specifications as listed below:
UTMI+ Low Pin Interface Specification (ULPI), Revision
1.1, October 20, 2004. http://www.ulpi.org
UTMI+ Specification, Revision 1.0, February 22, 2004.
ULPI Bus
A description of the ULPI pin signals are given in Table
During
synchronous
mode,
all
signals
are
synchronous to CLOCK. Using the ULPI bus, the link
controller can perform register reads and writes and
transmit data on the USB bus. The FUSB2805 uses the
ULPI bus to send status information, decoded USB
data, and register contents to the link controller. During
low-power
and
serial
modes,
all
signals
are
asynchronous to CLOCK, even if the clock is running.
An example of ULPI bus usage is shown in Figure 8.
Table 5.
ULPI Signal Description
Signal
Name
Direction on
FUSB2805
Signal Description
CLOCK
OUT
60 MHz interface clock.
If a clock is attached on CLKIN, the FUSB2805 drives a 60 MHz output clock.
During low-power and serial modes, the clock can be turned off to save power.
D0-D7
I/O
8-bit data bus.
In synchronous (SDR) mode, the link drives D0-D7 LOW by default. The link initiates
transfers by sending a non-zero data pattern called a TXCMD (transmit command). In
synchronous mode, the direction of D0-D7 is controlled by DIR. Contents of the D0-D7
lines must be ignored for exactly one clock cycle whenever DIR changes value; called
a
“turnaround” cycle.
The data lines have fixed directions and different meanings in low-power, 6-pin, and
3-pin serial modes.
DIR
OUT
Controls the direction of the D0-D7 data bus.
In synchronous (SDR) mode, the FUSB2805 drives DIR LOW by default, making the
data bus an input so the FUSB2805 can listen for TXCMDs from the link controller.
The FUSB2805 drives DIR HIGH only when it has data for the link. When DIR and NXT
are both HIGH, the byte on the data bus contains decoded USB data. When DIR is
HIGH and NXT is LOW, the byte contains status information called an RXCMD (receive
command). The only exception is when the FUSB2805 returns register-read data,
where NXT is also LOW, replacing the usual RXCMD byte. Every change in DIR
causes a turnaround cycle on the data bus, during which D0-D7 are not valid and must
be ignored by the link.
DIR is always asserted during low-power, 6-pin, 3-pin, and serial modes.
STP
IN
Stop.
In synchronous (SDR) mode, the link drives STP HIGH for one cycle after the last byte
of data sent to the FUSB2805. The link can optionally assert STP to force DIR to be
de-asserted.
In low-power and serial modes, the link holds STP HIGH to wake up the FUSB2805,
causing the ULPI bus to return to synchronous mode.
NXT
OUT
Next.
In synchronous (SDR) mode, the FUSB2805 drives NXT HIGH to throttle data. If DIR is
LOW, the FUSB2805 asserts NXT to tell the link controller to place the next data byte
on D0-D7 in the following clock cycle. If DIR is HIGH, the FUSB2805 asserts NXT to
tell the link controller a valid USB data byte is on D0-D7 in the current cycle. The
FUSB2805 always drives an RXCMD when DIR is HIGH and NXT is LOW, unless
register-read data is to be returned to the link controller in the current cycle.
NXT is not used in low-power or serial modes.
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