参数资料
型号: GE28F008B3BA70
厂商: INTEL CORP
元件分类: PROM
英文描述: 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46
封装: VFBGA-46
文件页数: 2/70页
文件大小: 1215K
代理商: GE28F008B3BA70
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
10
Datasheet
3.1
Architecture Diagram
3.2
Memory Maps and Block Organization
The B3 flash memory device is an asymmetrically blocked architecture that enables system
integration of code and data within a single flash device. Each block can be erased independently
of the others up to 100,000 times. For the address locations of each block, see the following
memory maps:
3.2.1
Parameter Blocks
The B3 flash memory device architecture includes parameter blocks to facilitate storage of
frequently updated small parameters (i.e., data that would normally be stored in an EEPROM). The
word-rewrite functionality of EEPROMs can be emulated using software techniques. Each device
contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096 words) each.
Figure 1. B3 Architecture Block Diagram
O
ut
put
M
ul
tip
le
xe
r
4-
K
W
or
d
P
ara
m
ete
rB
lo
ck
32-
KW
or
d
Ma
in
B
lo
ck
32-
KW
or
d
Ma
in
B
lo
ck
4-
K
W
or
d
P
ara
m
ete
rB
lo
ck
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
Da
ta
Regi
st
er
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
Input Buffer
Output Buffer
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
Command
User
Interface
Input Buffer
A
0-A19
DQ
0-DQ15
V
CCQ
WP#
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